1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a78c.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20#if WORKAROUND_CVE_2022_23960 21 wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c 22#endif /* WORKAROUND_CVE_2022_23960 */ 23 24cpu_reset_prologue cortex_a78c 25 26/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 27workaround_reset_start cortex_a78c, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 28 sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, BIT(46) 29workaround_reset_end cortex_a78c, CVE(2024, 5660) 30 31check_erratum_ls cortex_a78c, CVE(2024, 5660), CPU_REV(0, 2) 32 33workaround_reset_start cortex_a78c, ERRATUM(1827430), ERRATA_A78C_1827430 34 /* Disable allocation of splintered pages in the L2 TLB */ 35 sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN 36workaround_reset_end cortex_a78c, ERRATUM(1827430) 37 38check_erratum_ls cortex_a78c, ERRATUM(1827430), CPU_REV(0, 0) 39 40workaround_reset_start cortex_a78c, ERRATUM(1827440), ERRATA_A78C_1827440 41 /* Force Atomic Store to WB memory be done in L1 data cache */ 42 sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, BIT(2) 43workaround_reset_end cortex_a78c, ERRATUM(1827440) 44 45check_erratum_ls cortex_a78c, ERRATUM(1827440), CPU_REV(0, 0) 46 47workaround_reset_start cortex_a78c, ERRATUM(2132064), ERRATA_A78C_2132064 48 /* -------------------------------------------------------- 49 * Place the data prefetcher in the most conservative mode 50 * to reduce prefetches by writing the following bits to 51 * the value indicated: ecltr[7:6], PF_MODE = 2'b11 52 * -------------------------------------------------------- 53 */ 54 sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, (CORTEX_A78C_CPUECTLR_EL1_BIT_6 | CORTEX_A78C_CPUECTLR_EL1_BIT_7) 55workaround_reset_end cortex_a78c, ERRATUM(2132064) 56 57check_erratum_range cortex_a78c, ERRATUM(2132064), CPU_REV(0, 1), CPU_REV(0, 2) 58 59workaround_reset_start cortex_a78c, ERRATUM(2242638), ERRATA_A78C_2242638 60 ldr x0, =0x5 61 msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0 62 ldr x0, =0x10F600E000 63 msr CORTEX_A78C_IMP_CPUPOR_EL3, x0 64 ldr x0, =0x10FF80E000 65 msr CORTEX_A78C_IMP_CPUPMR_EL3, x0 66 ldr x0, =0x80000000003FF 67 msr CORTEX_A78C_IMP_CPUPCR_EL3, x0 68workaround_reset_end cortex_a78c, ERRATUM(2242638) 69 70check_erratum_range cortex_a78c, ERRATUM(2242638), CPU_REV(0, 1), CPU_REV(0, 2) 71 72workaround_reset_start cortex_a78c, ERRATUM(2376749), ERRATA_A78C_2376749 73 sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, CORTEX_A78C_CPUACTLR2_EL1_BIT_0 74workaround_reset_end cortex_a78c, ERRATUM(2376749) 75 76check_erratum_range cortex_a78c, ERRATUM(2376749), CPU_REV(0, 1), CPU_REV(0, 2) 77 78workaround_reset_start cortex_a78c, ERRATUM(2395411), ERRATA_A78C_2395411 79 sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, CORTEX_A78C_CPUACTLR2_EL1_BIT_40 80workaround_reset_end cortex_a78c, ERRATUM(2395411) 81 82check_erratum_range cortex_a78c, ERRATUM(2395411), CPU_REV(0, 1), CPU_REV(0, 2) 83 84workaround_reset_start cortex_a78c, ERRATUM(2683027), ERRATA_A78C_2683027 85 ldr x0, =0x3 86 msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0 87 ldr x0, =0xEE010F10 88 msr CORTEX_A78C_IMP_CPUPOR_EL3, x0 89 ldr x0, =0xFF1F0FFE 90 msr CORTEX_A78C_IMP_CPUPMR_EL3, x0 91 ldr x0, =0x100000004003FF 92 msr CORTEX_A78C_IMP_CPUPCR_EL3, x0 93workaround_reset_end cortex_a78c, ERRATUM(2683027) 94 95check_erratum_range cortex_a78c, ERRATUM(2683027), CPU_REV(0, 1), CPU_REV(0, 2) 96 97workaround_reset_start cortex_a78c, ERRATUM(2743232), ERRATA_A78C_2743232 98 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 99 sysreg_bit_set CORTEX_A78C_ACTLR5_EL1, BIT(55) 100 sysreg_bit_clear CORTEX_A78C_ACTLR5_EL1, BIT(56) 101workaround_reset_end cortex_a78c, ERRATUM(2743232) 102 103check_erratum_range cortex_a78c, ERRATUM(2743232), CPU_REV(0, 1), CPU_REV(0, 2) 104 105workaround_runtime_start cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121 106 /* dsb before isb of power down sequence */ 107 dsb sy 108workaround_runtime_end cortex_a78c, ERRATUM(2772121) 109 110check_erratum_ls cortex_a78c, ERRATUM(2772121), CPU_REV(0, 2) 111 112workaround_reset_start cortex_a78c, ERRATUM(2779484), ERRATA_A78C_2779484 113 sysreg_bit_set CORTEX_A78C_ACTLR3_EL1, BIT(47) 114workaround_reset_end cortex_a78c, ERRATUM(2779484) 115 116check_erratum_range cortex_a78c, ERRATUM(2779484), CPU_REV(0, 1), CPU_REV(0, 2) 117 118check_erratum_chosen cortex_a78c, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 119 120workaround_reset_start cortex_a78c, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 121#if IMAGE_BL31 122 /* 123 * The Cortex-A78c generic vectors are overridden to apply errata 124 * mitigation on exception entry from lower ELs. 125 */ 126 override_vector_table wa_cve_vbar_cortex_a78c 127#endif /* IMAGE_BL31 */ 128workaround_reset_end cortex_a78c, CVE(2022, 23960) 129 130cpu_reset_func_start cortex_a78c 131cpu_reset_func_end cortex_a78c 132 133 /* ---------------------------------------------------- 134 * HW will do the cache maintenance while powering down 135 * ---------------------------------------------------- 136 */ 137func cortex_a78c_core_pwr_dwn 138 /* --------------------------------------------------- 139 * Enable CPU power down bit in power control register 140 * --------------------------------------------------- 141 */ 142 sysreg_bit_set CORTEX_A78C_CPUPWRCTLR_EL1, CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 143 144 apply_erratum cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121, NO_GET_CPU_REV 145 146 isb 147 ret 148endfunc cortex_a78c_core_pwr_dwn 149 150 /* --------------------------------------------- 151 * This function provides cortex_a78c specific 152 * register information for crash reporting. 153 * It needs to return with x6 pointing to 154 * a list of register names in ascii and 155 * x8 - x15 having values of registers to be 156 * reported. 157 * --------------------------------------------- 158 */ 159.section .rodata.cortex_a78c_regs, "aS" 160cortex_a78c_regs: /* The ascii list of register names to be reported */ 161 .asciz "cpuectlr_el1", "" 162 163func cortex_a78c_cpu_reg_dump 164 adr x6, cortex_a78c_regs 165 mrs x8, CORTEX_A78C_CPUECTLR_EL1 166 ret 167endfunc cortex_a78c_cpu_reg_dump 168 169declare_cpu_ops cortex_a78c, CORTEX_A78C_MIDR, \ 170 cortex_a78c_reset_func, \ 171 cortex_a78c_core_pwr_dwn 172