1/* 2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a78c.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20#if WORKAROUND_CVE_2022_23960 21 wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c 22#endif /* WORKAROUND_CVE_2022_23960 */ 23 24workaround_reset_start cortex_a78c, ERRATUM(1827430), ERRATA_A78C_1827430 25 /* Disable allocation of splintered pages in the L2 TLB */ 26 sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN 27workaround_reset_end cortex_a78c, ERRATUM(1827430) 28 29check_erratum_ls cortex_a78c, ERRATUM(1827430), CPU_REV(0, 0) 30 31workaround_reset_start cortex_a78c, ERRATUM(1827440), ERRATA_A78C_1827440 32 /* Force Atomic Store to WB memory be done in L1 data cache */ 33 sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, BIT(2) 34workaround_reset_end cortex_a78c, ERRATUM(1827440) 35 36check_erratum_ls cortex_a78c, ERRATUM(1827440), CPU_REV(0, 0) 37 38workaround_reset_start cortex_a78c, ERRATUM(2132064), ERRATA_A78C_2132064 39 /* -------------------------------------------------------- 40 * Place the data prefetcher in the most conservative mode 41 * to reduce prefetches by writing the following bits to 42 * the value indicated: ecltr[7:6], PF_MODE = 2'b11 43 * -------------------------------------------------------- 44 */ 45 sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, (CORTEX_A78C_CPUECTLR_EL1_BIT_6 | CORTEX_A78C_CPUECTLR_EL1_BIT_7) 46workaround_reset_end cortex_a78c, ERRATUM(2132064) 47 48check_erratum_range cortex_a78c, ERRATUM(2132064), CPU_REV(0, 1), CPU_REV(0, 2) 49 50workaround_reset_start cortex_a78c, ERRATUM(2242638), ERRATA_A78C_2242638 51 ldr x0, =0x5 52 msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0 53 ldr x0, =0x10F600E000 54 msr CORTEX_A78C_IMP_CPUPOR_EL3, x0 55 ldr x0, =0x10FF80E000 56 msr CORTEX_A78C_IMP_CPUPMR_EL3, x0 57 ldr x0, =0x80000000003FF 58 msr CORTEX_A78C_IMP_CPUPCR_EL3, x0 59workaround_reset_end cortex_a78c, ERRATUM(2242638) 60 61check_erratum_range cortex_a78c, ERRATUM(2242638), CPU_REV(0, 1), CPU_REV(0, 2) 62 63workaround_reset_start cortex_a78c, ERRATUM(2376749), ERRATA_A78C_2376749 64 sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, CORTEX_A78C_CPUACTLR2_EL1_BIT_0 65workaround_reset_end cortex_a78c, ERRATUM(2376749) 66 67check_erratum_range cortex_a78c, ERRATUM(2376749), CPU_REV(0, 1), CPU_REV(0, 2) 68 69workaround_reset_start cortex_a78c, ERRATUM(2395411), ERRATA_A78C_2395411 70 sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, CORTEX_A78C_CPUACTLR2_EL1_BIT_40 71workaround_reset_end cortex_a78c, ERRATUM(2395411) 72 73check_erratum_range cortex_a78c, ERRATUM(2395411), CPU_REV(0, 1), CPU_REV(0, 2) 74 75workaround_reset_start cortex_a78c, ERRATUM(2743232), ERRATA_A78C_2743232 76 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 77 sysreg_bit_set CORTEX_A78C_ACTLR5_EL1, BIT(55) 78 sysreg_bit_clear CORTEX_A78C_ACTLR5_EL1, BIT(56) 79workaround_reset_end cortex_a78c, ERRATUM(2743232) 80 81check_erratum_range cortex_a78c, ERRATUM(2743232), CPU_REV(0, 1), CPU_REV(0, 2) 82 83workaround_runtime_start cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121 84 /* dsb before isb of power down sequence */ 85 dsb sy 86workaround_runtime_end cortex_a78c, ERRATUM(2772121) 87 88check_erratum_ls cortex_a78c, ERRATUM(2772121), CPU_REV(0, 2) 89 90workaround_reset_start cortex_a78c, ERRATUM(2779484), ERRATA_A78C_2779484 91 sysreg_bit_set CORTEX_A78C_ACTLR3_EL1, BIT(47) 92workaround_reset_end cortex_a78c, ERRATUM(2779484) 93 94check_erratum_range cortex_a78c, ERRATUM(2779484), CPU_REV(0, 1), CPU_REV(0, 2) 95 96check_erratum_chosen cortex_a78c, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 97 98workaround_reset_start cortex_a78c, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 99#if IMAGE_BL31 100 /* 101 * The Cortex-A78c generic vectors are overridden to apply errata 102 * mitigation on exception entry from lower ELs. 103 */ 104 override_vector_table wa_cve_vbar_cortex_a78c 105#endif /* IMAGE_BL31 */ 106workaround_reset_end cortex_a78c, CVE(2022, 23960) 107 108cpu_reset_func_start cortex_a78c 109cpu_reset_func_end cortex_a78c 110 111errata_report_shim cortex_a78c 112 113 /* ---------------------------------------------------- 114 * HW will do the cache maintenance while powering down 115 * ---------------------------------------------------- 116 */ 117func cortex_a78c_core_pwr_dwn 118 /* --------------------------------------------------- 119 * Enable CPU power down bit in power control register 120 * --------------------------------------------------- 121 */ 122 sysreg_bit_set CORTEX_A78C_CPUPWRCTLR_EL1, CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 123 124 apply_erratum cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121 125 126 isb 127 ret 128endfunc cortex_a78c_core_pwr_dwn 129 130 /* --------------------------------------------- 131 * This function provides cortex_a78c specific 132 * register information for crash reporting. 133 * It needs to return with x6 pointing to 134 * a list of register names in ascii and 135 * x8 - x15 having values of registers to be 136 * reported. 137 * --------------------------------------------- 138 */ 139.section .rodata.cortex_a78c_regs, "aS" 140cortex_a78c_regs: /* The ascii list of register names to be reported */ 141 .asciz "cpuectlr_el1", "" 142 143func cortex_a78c_cpu_reg_dump 144 adr x6, cortex_a78c_regs 145 mrs x8, CORTEX_A78C_CPUECTLR_EL1 146 ret 147endfunc cortex_a78c_cpu_reg_dump 148 149declare_cpu_ops cortex_a78c, CORTEX_A78C_MIDR, \ 150 cortex_a78c_reset_func, \ 151 cortex_a78c_core_pwr_dwn 152