1/* 2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a78c.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* -------------------------------------------------- 21 * Errata Workaround for Cortex A78C Erratum 2376749. 22 * This applies to revision r0p1 and r0p2 of the A78C 23 * and is currently open. It is a Cat B erratum. 24 * Inputs: 25 * x0: variant[4:7] and revision[0:3] of current cpu. 26 * Shall clobber: x0-x4, x17 27 * -------------------------------------------------- 28 */ 29func errata_a78c_2376749_wa 30 /* Check revision */ 31 mov x17, x30 32 bl check_errata_2376749 33 cbz x0, 1f 34 /* Set CPUACTLR2_EL1[0] to 1. */ 35 mrs x1, CORTEX_A78C_CPUACTLR2_EL1 36 orr x1, x1, #CORTEX_A78C_CPUACTLR2_EL1_BIT_0 37 msr CORTEX_A78C_CPUACTLR2_EL1, x1 381: 39 ret x17 40endfunc errata_a78c_2376749_wa 41 42func check_errata_2376749 43 /* Applies to r0p1 and r0p2*/ 44 mov x1, #0x01 45 mov x2, #0x02 46 b cpu_rev_var_range 47endfunc check_errata_2376749 48 49/* -------------------------------------------------- 50 * Errata Workaround for Cortex A78C Erratum 2395411. 51 * This applies to revision r0p1 and r0p2 of the A78C 52 * and is currently open. It is a Cat B erratum. 53 * Inputs: 54 * x0: variant[4:7] and revision[0:3] of current cpu. 55 * Shall clobber: x0-x4, x17 56 * -------------------------------------------------- 57 */ 58func errata_a78c_2395411_wa 59 /* Check revision. */ 60 mov x17, x30 61 bl check_errata_2395411 62 cbz x0, 1f 63 64 /* Set CPUACTRL2_EL1[40] to 1. */ 65 mrs x1, CORTEX_A78C_CPUACTLR2_EL1 66 orr x1, x1, #CORTEX_A78C_CPUACTLR2_EL1_BIT_40 67 msr CORTEX_A78C_CPUACTLR2_EL1, x1 681: 69 ret x17 70endfunc errata_a78c_2395411_wa 71 72func check_errata_2395411 73 /* Applies to r0p1 and r0p2 */ 74 mov x1, #0x01 75 mov x2, #0x02 76 b cpu_rev_var_range 77endfunc check_errata_2395411 78 79#if WORKAROUND_CVE_2022_23960 80 wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c 81#endif /* WORKAROUND_CVE_2022_23960 */ 82 83/* -------------------------------------------------- 84 * Errata Workaround for A78C Erratum 2132064. 85 * This applies to revisions r0p1 and r0p2 of A78C 86 * and is still open. 87 * Inputs: 88 * x0: variant[4:7] and revision[0:3] of current cpu. 89 * Shall clobber: x0-x17 90 * -------------------------------------------------- 91 */ 92func errata_a78c_2132064_wa 93 /* Compare x0 against revisions r0p0 - r0p1 */ 94 mov x17, x30 95 bl check_errata_2132064 96 cbz x0, 1f 97 98 /* -------------------------------------------------------- 99 * Place the data prefetcher in the most conservative mode 100 * to reduce prefetches by writing the following bits to 101 * the value indicated: ecltr[7:6], PF_MODE = 2'b11 102 * -------------------------------------------------------- 103 */ 104 mrs x0, CORTEX_A78C_CPUECTLR_EL1 105 orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT_6 106 orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT_7 107 msr CORTEX_A78C_CPUECTLR_EL1, x0 108 isb 1091: 110 ret x17 111endfunc errata_a78c_2132064_wa 112 113func check_errata_2132064 114 /* Applies to revisions r0p1 and r0p2. */ 115 mov x1, #CPU_REV(0, 1) 116 mov x2, #CPU_REV(0, 2) 117 b cpu_rev_var_range 118endfunc check_errata_2132064 119 120/* ---------------------------------------------------------- 121 * Errata Workaround for A78C Erratum 2242638. 122 * This applies to revisions r0p1 and r0p2 of the Cortex A78C 123 * processor and is still open. 124 * x0: variant[4:7] and revision[0:3] of current cpu. 125 * Shall clobber: x0-x17 126 * ---------------------------------------------------------- 127 */ 128func errata_a78c_2242638_wa 129 /* Compare x0 against revisions r0p1 - r0p2 */ 130 mov x17, x30 131 bl check_errata_2242638 132 cbz x0, 1f 133 134 ldr x0, =0x5 135 msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0 136 ldr x0, =0x10F600E000 137 msr CORTEX_A78C_IMP_CPUPOR_EL3, x0 138 ldr x0, =0x10FF80E000 139 msr CORTEX_A78C_IMP_CPUPMR_EL3, x0 140 ldr x0, =0x80000000003FF 141 msr CORTEX_A78C_IMP_CPUPCR_EL3, x0 142 143 isb 1441: 145 ret x17 146endfunc errata_a78c_2242638_wa 147 148func check_errata_2242638 149 /* Applies to revisions r0p1-r0p2. */ 150 mov x1, #CPU_REV(0, 1) 151 mov x2, #CPU_REV(0, 2) 152 b cpu_rev_var_range 153endfunc check_errata_2242638 154 155/* ---------------------------------------------------------------- 156 * Errata Workaround for A78C Erratum 2772121. 157 * This applies to revisions r0p0, r0p1 and r0p2 of the Cortex A78C 158 * processor and is still open. 159 * x0: variant[4:7] and revision[0:3] of current cpu. 160 * Shall clobber: x0-x17 161 * ---------------------------------------------------------------- 162 */ 163func errata_a78c_2772121_wa 164 mov x17, x30 165 bl check_errata_2772121 166 cbz x0, 1f 167 168 /* dsb before isb of power down sequence */ 169 dsb sy 1701: 171 ret x17 172endfunc errata_a78c_2772121_wa 173 174func check_errata_2772121 175 /* Applies to all revisions <= r0p2 */ 176 mov x1, #0x02 177 b cpu_rev_var_ls 178endfunc check_errata_2772121 179 180/* -------------------------------------------------- 181 * Errata Workaround for Cortex A78C Errata 2779484. 182 * This applies to revisions r0p1 and r0p2. 183 * It is still open. 184 * x0: variant[4:7] and revision[0:3] of current cpu. 185 * Shall clobber: x0-x1, x17 186 * -------------------------------------------------- 187 */ 188func errata_a78c_2779484_wa 189 /* Check revision. */ 190 mov x17, x30 191 bl check_errata_2779484 192 cbz x0, 1f 193 194 /* Apply the workaround */ 195 mrs x1, CORTEX_A78C_ACTLR3_EL1 196 orr x1, x1, #BIT(47) 197 msr CORTEX_A78C_ACTLR3_EL1, x1 198 1991: 200 ret x17 201endfunc errata_a78c_2779484_wa 202 203func check_errata_2779484 204 /* Applies to r0p1 and r0p2*/ 205 mov x1, #0x01 206 mov x2, #0x02 207 b cpu_rev_var_range 208endfunc check_errata_2779484 209 210func check_errata_cve_2022_23960 211#if WORKAROUND_CVE_2022_23960 212 mov x0, #ERRATA_APPLIES 213#else 214 mov x0, #ERRATA_MISSING 215#endif 216 ret 217endfunc check_errata_cve_2022_23960 218 219 /* ------------------------------------------------- 220 * The CPU Ops reset function for Cortex-A78C 221 * ------------------------------------------------- 222 */ 223func cortex_a78c_reset_func 224 mov x19, x30 225 bl cpu_get_rev_var 226 mov x18, x0 227 228#if ERRATA_A78C_2132064 229 mov x0, x18 230 bl errata_a78c_2132064_wa 231#endif 232 233#if ERRATA_A78C_2242638 234 mov x0, x18 235 bl errata_a78c_2242638_wa 236#endif 237 238#if ERRATA_A78C_2376749 239 mov x0, x18 240 bl errata_a78c_2376749_wa 241#endif 242 243#if ERRATA_A78C_2395411 244 mov x0, x18 245 bl errata_a78c_2395411_wa 246#endif 247 248#if ERRATA_A78C_2779484 249 mov x0, x18 250 bl errata_a78c_2779484_wa 251#endif 252 253#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 254 /* 255 * The Cortex-A78c generic vectors are overridden to apply errata 256 * mitigation on exception entry from lower ELs. 257 */ 258 adr x0, wa_cve_vbar_cortex_a78c 259 msr vbar_el3, x0 260#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ 261 262 isb 263 ret x19 264endfunc cortex_a78c_reset_func 265 266 /* ---------------------------------------------------- 267 * HW will do the cache maintenance while powering down 268 * ---------------------------------------------------- 269 */ 270func cortex_a78c_core_pwr_dwn 271 /* --------------------------------------------------- 272 * Enable CPU power down bit in power control register 273 * --------------------------------------------------- 274 */ 275 mrs x0, CORTEX_A78C_CPUPWRCTLR_EL1 276 orr x0, x0, #CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 277 msr CORTEX_A78C_CPUPWRCTLR_EL1, x0 278#if ERRATA_A78C_2772121 279 mov x15, x30 280 bl cpu_get_rev_var 281 bl errata_a78c_2772121_wa 282 mov x30, x15 283#endif /* ERRATA_A78C_2772121 */ 284 isb 285 ret 286endfunc cortex_a78c_core_pwr_dwn 287 288#if REPORT_ERRATA 289/* 290 * Errata printing function for Cortex A78C. Must follow AAPCS. 291 */ 292func cortex_a78c_errata_report 293 stp x8, x30, [sp, #-16]! 294 295 bl cpu_get_rev_var 296 mov x8, x0 297 298 /* 299 * Report all errata. The revision-variant information is passed to 300 * checking functions of each errata. 301 */ 302 report_errata ERRATA_A78C_2132064, cortex_a78c, 2132064 303 report_errata ERRATA_A78C_2242638, cortex_a78c, 2242638 304 report_errata ERRATA_A78C_2376749, cortex_a78c, 2376749 305 report_errata ERRATA_A78C_2395411, cortex_a78c, 2395411 306 report_errata ERRATA_A78C_2772121, cortex_a78c, 2772121 307 report_errata ERRATA_A78C_2779484, cortex_a78c, 2779484 308 report_errata WORKAROUND_CVE_2022_23960, cortex_a78c, cve_2022_23960 309 310 ldp x8, x30, [sp], #16 311 ret 312endfunc cortex_a78c_errata_report 313#endif 314 315 /* --------------------------------------------- 316 * This function provides cortex_a78c specific 317 * register information for crash reporting. 318 * It needs to return with x6 pointing to 319 * a list of register names in ascii and 320 * x8 - x15 having values of registers to be 321 * reported. 322 * --------------------------------------------- 323 */ 324.section .rodata.cortex_a78c_regs, "aS" 325cortex_a78c_regs: /* The ascii list of register names to be reported */ 326 .asciz "cpuectlr_el1", "" 327 328func cortex_a78c_cpu_reg_dump 329 adr x6, cortex_a78c_regs 330 mrs x8, CORTEX_A78C_CPUECTLR_EL1 331 ret 332endfunc cortex_a78c_cpu_reg_dump 333 334declare_cpu_ops cortex_a78c, CORTEX_A78C_MIDR, \ 335 cortex_a78c_reset_func, \ 336 cortex_a78c_core_pwr_dwn 337