1/* 2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a78c.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* -------------------------------------------------- 21 * Errata Workaround for A78C Erratum 1827430. 22 * This applies to revision r0p0 of the Cortex A78C 23 * processor and is fixed in r0p1. 24 * x0: variant[4:7] and revision[0:3] of current cpu. 25 * Shall clobber: x0-x17 26 * -------------------------------------------------- 27 */ 28func errata_a78c_1827430_wa 29 mov x17, x30 30 bl check_errata_1827430 31 cbz x0, 1f 32 33 /* Disable allocation of splintered pages in the L2 TLB */ 34 mrs x1, CORTEX_A78C_CPUECTLR_EL1 35 orr x1, x1, CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN 36 msr CORTEX_A78C_CPUECTLR_EL1, x1 371: 38 ret x17 39endfunc errata_a78c_1827430_wa 40 41func check_errata_1827430 42 /* Applies to revision r0p0 only */ 43 mov x1, #0x00 44 b cpu_rev_var_ls 45endfunc check_errata_1827430 46 47/* -------------------------------------------------- 48 * Errata Workaround for Cortex A78C Erratum 2376749. 49 * This applies to revision r0p1 and r0p2 of the A78C 50 * and is currently open. It is a Cat B erratum. 51 * Inputs: 52 * x0: variant[4:7] and revision[0:3] of current cpu. 53 * Shall clobber: x0-x4, x17 54 * -------------------------------------------------- 55 */ 56func errata_a78c_2376749_wa 57 /* Check revision */ 58 mov x17, x30 59 bl check_errata_2376749 60 cbz x0, 1f 61 /* Set CPUACTLR2_EL1[0] to 1. */ 62 mrs x1, CORTEX_A78C_CPUACTLR2_EL1 63 orr x1, x1, #CORTEX_A78C_CPUACTLR2_EL1_BIT_0 64 msr CORTEX_A78C_CPUACTLR2_EL1, x1 651: 66 ret x17 67endfunc errata_a78c_2376749_wa 68 69func check_errata_2376749 70 /* Applies to r0p1 and r0p2*/ 71 mov x1, #0x01 72 mov x2, #0x02 73 b cpu_rev_var_range 74endfunc check_errata_2376749 75 76/* -------------------------------------------------- 77 * Errata Workaround for Cortex A78C Erratum 2395411. 78 * This applies to revision r0p1 and r0p2 of the A78C 79 * and is currently open. It is a Cat B erratum. 80 * Inputs: 81 * x0: variant[4:7] and revision[0:3] of current cpu. 82 * Shall clobber: x0-x4, x17 83 * -------------------------------------------------- 84 */ 85func errata_a78c_2395411_wa 86 /* Check revision. */ 87 mov x17, x30 88 bl check_errata_2395411 89 cbz x0, 1f 90 91 /* Set CPUACTRL2_EL1[40] to 1. */ 92 mrs x1, CORTEX_A78C_CPUACTLR2_EL1 93 orr x1, x1, #CORTEX_A78C_CPUACTLR2_EL1_BIT_40 94 msr CORTEX_A78C_CPUACTLR2_EL1, x1 951: 96 ret x17 97endfunc errata_a78c_2395411_wa 98 99func check_errata_2395411 100 /* Applies to r0p1 and r0p2 */ 101 mov x1, #0x01 102 mov x2, #0x02 103 b cpu_rev_var_range 104endfunc check_errata_2395411 105 106#if WORKAROUND_CVE_2022_23960 107 wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c 108#endif /* WORKAROUND_CVE_2022_23960 */ 109 110/* -------------------------------------------------- 111 * Errata Workaround for A78C Erratum 2132064. 112 * This applies to revisions r0p1 and r0p2 of A78C 113 * and is still open. 114 * Inputs: 115 * x0: variant[4:7] and revision[0:3] of current cpu. 116 * Shall clobber: x0-x17 117 * -------------------------------------------------- 118 */ 119func errata_a78c_2132064_wa 120 /* Compare x0 against revisions r0p0 - r0p1 */ 121 mov x17, x30 122 bl check_errata_2132064 123 cbz x0, 1f 124 125 /* -------------------------------------------------------- 126 * Place the data prefetcher in the most conservative mode 127 * to reduce prefetches by writing the following bits to 128 * the value indicated: ecltr[7:6], PF_MODE = 2'b11 129 * -------------------------------------------------------- 130 */ 131 mrs x0, CORTEX_A78C_CPUECTLR_EL1 132 orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT_6 133 orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT_7 134 msr CORTEX_A78C_CPUECTLR_EL1, x0 135 isb 1361: 137 ret x17 138endfunc errata_a78c_2132064_wa 139 140func check_errata_2132064 141 /* Applies to revisions r0p1 and r0p2. */ 142 mov x1, #CPU_REV(0, 1) 143 mov x2, #CPU_REV(0, 2) 144 b cpu_rev_var_range 145endfunc check_errata_2132064 146 147/* ---------------------------------------------------------- 148 * Errata Workaround for A78C Erratum 2242638. 149 * This applies to revisions r0p1 and r0p2 of the Cortex A78C 150 * processor and is still open. 151 * x0: variant[4:7] and revision[0:3] of current cpu. 152 * Shall clobber: x0-x17 153 * ---------------------------------------------------------- 154 */ 155func errata_a78c_2242638_wa 156 /* Compare x0 against revisions r0p1 - r0p2 */ 157 mov x17, x30 158 bl check_errata_2242638 159 cbz x0, 1f 160 161 ldr x0, =0x5 162 msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0 163 ldr x0, =0x10F600E000 164 msr CORTEX_A78C_IMP_CPUPOR_EL3, x0 165 ldr x0, =0x10FF80E000 166 msr CORTEX_A78C_IMP_CPUPMR_EL3, x0 167 ldr x0, =0x80000000003FF 168 msr CORTEX_A78C_IMP_CPUPCR_EL3, x0 169 170 isb 1711: 172 ret x17 173endfunc errata_a78c_2242638_wa 174 175func check_errata_2242638 176 /* Applies to revisions r0p1-r0p2. */ 177 mov x1, #CPU_REV(0, 1) 178 mov x2, #CPU_REV(0, 2) 179 b cpu_rev_var_range 180endfunc check_errata_2242638 181 182/* ---------------------------------------------------------------- 183 * Errata Workaround for A78C Erratum 2772121. 184 * This applies to revisions r0p0, r0p1 and r0p2 of the Cortex A78C 185 * processor and is still open. 186 * x0: variant[4:7] and revision[0:3] of current cpu. 187 * Shall clobber: x0-x17 188 * ---------------------------------------------------------------- 189 */ 190func errata_a78c_2772121_wa 191 mov x17, x30 192 bl check_errata_2772121 193 cbz x0, 1f 194 195 /* dsb before isb of power down sequence */ 196 dsb sy 1971: 198 ret x17 199endfunc errata_a78c_2772121_wa 200 201func check_errata_2772121 202 /* Applies to all revisions <= r0p2 */ 203 mov x1, #0x02 204 b cpu_rev_var_ls 205endfunc check_errata_2772121 206 207/* -------------------------------------------------- 208 * Errata Workaround for Cortex A78C Errata 2779484. 209 * This applies to revisions r0p1 and r0p2. 210 * It is still open. 211 * x0: variant[4:7] and revision[0:3] of current cpu. 212 * Shall clobber: x0-x1, x17 213 * -------------------------------------------------- 214 */ 215func errata_a78c_2779484_wa 216 /* Check revision. */ 217 mov x17, x30 218 bl check_errata_2779484 219 cbz x0, 1f 220 221 /* Apply the workaround */ 222 mrs x1, CORTEX_A78C_ACTLR3_EL1 223 orr x1, x1, #BIT(47) 224 msr CORTEX_A78C_ACTLR3_EL1, x1 225 2261: 227 ret x17 228endfunc errata_a78c_2779484_wa 229 230func check_errata_2779484 231 /* Applies to r0p1 and r0p2*/ 232 mov x1, #0x01 233 mov x2, #0x02 234 b cpu_rev_var_range 235endfunc check_errata_2779484 236 237func check_errata_cve_2022_23960 238#if WORKAROUND_CVE_2022_23960 239 mov x0, #ERRATA_APPLIES 240#else 241 mov x0, #ERRATA_MISSING 242#endif 243 ret 244endfunc check_errata_cve_2022_23960 245 246 /* ------------------------------------------------- 247 * The CPU Ops reset function for Cortex-A78C 248 * ------------------------------------------------- 249 */ 250func cortex_a78c_reset_func 251 mov x19, x30 252 bl cpu_get_rev_var 253 mov x18, x0 254 255#if ERRATA_A78C_1827430 256 mov x0, x18 257 bl errata_a78c_1827430_wa 258#endif 259 260#if ERRATA_A78C_2132064 261 mov x0, x18 262 bl errata_a78c_2132064_wa 263#endif 264 265#if ERRATA_A78C_2242638 266 mov x0, x18 267 bl errata_a78c_2242638_wa 268#endif 269 270#if ERRATA_A78C_2376749 271 mov x0, x18 272 bl errata_a78c_2376749_wa 273#endif 274 275#if ERRATA_A78C_2395411 276 mov x0, x18 277 bl errata_a78c_2395411_wa 278#endif 279 280#if ERRATA_A78C_2779484 281 mov x0, x18 282 bl errata_a78c_2779484_wa 283#endif 284 285#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 286 /* 287 * The Cortex-A78c generic vectors are overridden to apply errata 288 * mitigation on exception entry from lower ELs. 289 */ 290 adr x0, wa_cve_vbar_cortex_a78c 291 msr vbar_el3, x0 292#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ 293 294 isb 295 ret x19 296endfunc cortex_a78c_reset_func 297 298 /* ---------------------------------------------------- 299 * HW will do the cache maintenance while powering down 300 * ---------------------------------------------------- 301 */ 302func cortex_a78c_core_pwr_dwn 303 /* --------------------------------------------------- 304 * Enable CPU power down bit in power control register 305 * --------------------------------------------------- 306 */ 307 mrs x0, CORTEX_A78C_CPUPWRCTLR_EL1 308 orr x0, x0, #CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 309 msr CORTEX_A78C_CPUPWRCTLR_EL1, x0 310#if ERRATA_A78C_2772121 311 mov x15, x30 312 bl cpu_get_rev_var 313 bl errata_a78c_2772121_wa 314 mov x30, x15 315#endif /* ERRATA_A78C_2772121 */ 316 isb 317 ret 318endfunc cortex_a78c_core_pwr_dwn 319 320#if REPORT_ERRATA 321/* 322 * Errata printing function for Cortex A78C. Must follow AAPCS. 323 */ 324func cortex_a78c_errata_report 325 stp x8, x30, [sp, #-16]! 326 327 bl cpu_get_rev_var 328 mov x8, x0 329 330 /* 331 * Report all errata. The revision-variant information is passed to 332 * checking functions of each errata. 333 */ 334 report_errata ERRATA_A78C_1827430, cortex_a78c, 1827430 335 report_errata ERRATA_A78C_2132064, cortex_a78c, 2132064 336 report_errata ERRATA_A78C_2242638, cortex_a78c, 2242638 337 report_errata ERRATA_A78C_2376749, cortex_a78c, 2376749 338 report_errata ERRATA_A78C_2395411, cortex_a78c, 2395411 339 report_errata ERRATA_A78C_2772121, cortex_a78c, 2772121 340 report_errata ERRATA_A78C_2779484, cortex_a78c, 2779484 341 report_errata WORKAROUND_CVE_2022_23960, cortex_a78c, cve_2022_23960 342 343 ldp x8, x30, [sp], #16 344 ret 345endfunc cortex_a78c_errata_report 346#endif 347 348 /* --------------------------------------------- 349 * This function provides cortex_a78c specific 350 * register information for crash reporting. 351 * It needs to return with x6 pointing to 352 * a list of register names in ascii and 353 * x8 - x15 having values of registers to be 354 * reported. 355 * --------------------------------------------- 356 */ 357.section .rodata.cortex_a78c_regs, "aS" 358cortex_a78c_regs: /* The ascii list of register names to be reported */ 359 .asciz "cpuectlr_el1", "" 360 361func cortex_a78c_cpu_reg_dump 362 adr x6, cortex_a78c_regs 363 mrs x8, CORTEX_A78C_CPUECTLR_EL1 364 ret 365endfunc cortex_a78c_cpu_reg_dump 366 367declare_cpu_ops cortex_a78c, CORTEX_A78C_MIDR, \ 368 cortex_a78c_reset_func, \ 369 cortex_a78c_core_pwr_dwn 370