1/* 2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a78c.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20#if WORKAROUND_CVE_2022_23960 21 wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c 22#endif /* WORKAROUND_CVE_2022_23960 */ 23 24workaround_reset_start cortex_a78c, ERRATUM(1827430), ERRATA_A78C_1827430 25 /* Disable allocation of splintered pages in the L2 TLB */ 26 mrs x1, CORTEX_A78C_CPUECTLR_EL1 27 orr x1, x1, CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN 28 msr CORTEX_A78C_CPUECTLR_EL1, x1 29workaround_reset_end cortex_a78c, ERRATUM(1827430) 30 31check_erratum_ls cortex_a78c, ERRATUM(1827430), CPU_REV(0, 0) 32 33workaround_reset_start cortex_a78c, ERRATUM(1827440), ERRATA_A78C_1827440 34 /* Force Atomic Store to WB memory be done in L1 data cache */ 35 mrs x1, CORTEX_A78C_CPUACTLR2_EL1 36 orr x1, x1, #BIT(2) 37 msr CORTEX_A78C_CPUACTLR2_EL1, x1 38workaround_reset_end cortex_a78c, ERRATUM(1827440) 39 40check_erratum_ls cortex_a78c, ERRATUM(1827440), CPU_REV(0, 0) 41 42workaround_reset_start cortex_a78c, ERRATUM(2132064), ERRATA_A78C_2132064 43 /* -------------------------------------------------------- 44 * Place the data prefetcher in the most conservative mode 45 * to reduce prefetches by writing the following bits to 46 * the value indicated: ecltr[7:6], PF_MODE = 2'b11 47 * -------------------------------------------------------- 48 */ 49 mrs x0, CORTEX_A78C_CPUECTLR_EL1 50 orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT_6 51 orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT_7 52 msr CORTEX_A78C_CPUECTLR_EL1, x0 53workaround_reset_end cortex_a78c, ERRATUM(2132064) 54 55check_erratum_range cortex_a78c, ERRATUM(2132064), CPU_REV(0, 1), CPU_REV(0, 2) 56 57workaround_reset_start cortex_a78c, ERRATUM(2242638), ERRATA_A78C_2242638 58 ldr x0, =0x5 59 msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0 60 ldr x0, =0x10F600E000 61 msr CORTEX_A78C_IMP_CPUPOR_EL3, x0 62 ldr x0, =0x10FF80E000 63 msr CORTEX_A78C_IMP_CPUPMR_EL3, x0 64 ldr x0, =0x80000000003FF 65 msr CORTEX_A78C_IMP_CPUPCR_EL3, x0 66workaround_reset_end cortex_a78c, ERRATUM(2242638) 67 68check_erratum_range cortex_a78c, ERRATUM(2242638), CPU_REV(0, 1), CPU_REV(0, 2) 69 70workaround_reset_start cortex_a78c, ERRATUM(2376749), ERRATA_A78C_2376749 71 /* Set CPUACTLR2_EL1[0] to 1. */ 72 mrs x1, CORTEX_A78C_CPUACTLR2_EL1 73 orr x1, x1, #CORTEX_A78C_CPUACTLR2_EL1_BIT_0 74 msr CORTEX_A78C_CPUACTLR2_EL1, x1 75workaround_reset_end cortex_a78c, ERRATUM(2376749) 76 77check_erratum_range cortex_a78c, ERRATUM(2376749), CPU_REV(0, 1), CPU_REV(0, 2) 78 79workaround_reset_start cortex_a78c, ERRATUM(2395411), ERRATA_A78C_2395411 80 /* Set CPUACTRL2_EL1[40] to 1. */ 81 mrs x1, CORTEX_A78C_CPUACTLR2_EL1 82 orr x1, x1, #CORTEX_A78C_CPUACTLR2_EL1_BIT_40 83 msr CORTEX_A78C_CPUACTLR2_EL1, x1 84workaround_reset_end cortex_a78c, ERRATUM(2395411) 85 86check_erratum_range cortex_a78c, ERRATUM(2395411), CPU_REV(0, 1), CPU_REV(0, 2) 87 88workaround_runtime_start cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121 89 /* dsb before isb of power down sequence */ 90 dsb sy 91workaround_runtime_end cortex_a78c, ERRATUM(2772121) 92 93check_erratum_ls cortex_a78c, ERRATUM(2772121), CPU_REV(0, 2) 94 95workaround_reset_start cortex_a78c, ERRATUM(2779484), ERRATA_A78C_2779484 96 /* Apply the workaround */ 97 mrs x1, CORTEX_A78C_ACTLR3_EL1 98 orr x1, x1, #BIT(47) 99 msr CORTEX_A78C_ACTLR3_EL1, x1 100workaround_reset_end cortex_a78c, ERRATUM(2779484) 101 102check_erratum_range cortex_a78c, ERRATUM(2779484), CPU_REV(0, 1), CPU_REV(0, 2) 103 104check_erratum_chosen cortex_a78c, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 105 106workaround_reset_start cortex_a78c, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 107#if IMAGE_BL31 108 /* 109 * The Cortex-A78c generic vectors are overridden to apply errata 110 * mitigation on exception entry from lower ELs. 111 */ 112 adr x0, wa_cve_vbar_cortex_a78c 113 msr vbar_el3, x0 114#endif /* IMAGE_BL31 */ 115workaround_reset_end cortex_a78c, CVE(2022, 23960) 116 117cpu_reset_func_start cortex_a78c 118cpu_reset_func_end cortex_a78c 119 120errata_report_shim cortex_a78c 121 122 /* ---------------------------------------------------- 123 * HW will do the cache maintenance while powering down 124 * ---------------------------------------------------- 125 */ 126func cortex_a78c_core_pwr_dwn 127 /* --------------------------------------------------- 128 * Enable CPU power down bit in power control register 129 * --------------------------------------------------- 130 */ 131 mrs x0, CORTEX_A78C_CPUPWRCTLR_EL1 132 orr x0, x0, #CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 133 msr CORTEX_A78C_CPUPWRCTLR_EL1, x0 134 135 apply_erratum cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121 136 137 isb 138 ret 139endfunc cortex_a78c_core_pwr_dwn 140 141 /* --------------------------------------------- 142 * This function provides cortex_a78c specific 143 * register information for crash reporting. 144 * It needs to return with x6 pointing to 145 * a list of register names in ascii and 146 * x8 - x15 having values of registers to be 147 * reported. 148 * --------------------------------------------- 149 */ 150.section .rodata.cortex_a78c_regs, "aS" 151cortex_a78c_regs: /* The ascii list of register names to be reported */ 152 .asciz "cpuectlr_el1", "" 153 154func cortex_a78c_cpu_reg_dump 155 adr x6, cortex_a78c_regs 156 mrs x8, CORTEX_A78C_CPUECTLR_EL1 157 ret 158endfunc cortex_a78c_cpu_reg_dump 159 160declare_cpu_ops cortex_a78c, CORTEX_A78C_MIDR, \ 161 cortex_a78c_reset_func, \ 162 cortex_a78c_core_pwr_dwn 163