1/* 2 * Copyright (c) 2021-2022, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a78c.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* -------------------------------------------------- 21 * Errata Workaround for Cortex A78C Erratum 2395411. 22 * This applies to revision r0p1 and r0p2 of the A78C 23 * and is currently open. It is a Cat B erratum. 24 * Inputs: 25 * x0: variant[4:7] and revision[0:3] of current cpu. 26 * Shall clobber: x0-x4, x17 27 * -------------------------------------------------- 28 */ 29func errata_a78c_2395411_wa 30 /* Check revision. */ 31 mov x17, x30 32 bl check_errata_2395411 33 cbz x0, 1f 34 35 /* Set CPUACTRL2_EL1[40] to 1. */ 36 mrs x1, CORTEX_A78C_CPUACTLR2_EL1 37 orr x1, x1, #CORTEX_A78C_CPUACTLR2_EL1_BIT_40 38 msr CORTEX_A78C_CPUACTLR2_EL1, x1 391: 40 ret x17 41endfunc errata_a78c_2395411_wa 42 43func check_errata_2395411 44 /* Applies to r0p1 and r0p2 */ 45 mov x1, #0x01 46 mov x2, #0x02 47 b cpu_rev_var_range 48endfunc check_errata_2395411 49 50#if WORKAROUND_CVE_2022_23960 51 wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c 52#endif /* WORKAROUND_CVE_2022_23960 */ 53 54/* -------------------------------------------------- 55 * Errata Workaround for A78C Erratum 2132064. 56 * This applies to revisions r0p1 and r0p2 of A78C 57 * and is still open. 58 * Inputs: 59 * x0: variant[4:7] and revision[0:3] of current cpu. 60 * Shall clobber: x0-x17 61 * -------------------------------------------------- 62 */ 63func errata_a78c_2132064_wa 64 /* Compare x0 against revisions r0p0 - r0p1 */ 65 mov x17, x30 66 bl check_errata_2132064 67 cbz x0, 1f 68 69 /* -------------------------------------------------------- 70 * Place the data prefetcher in the most conservative mode 71 * to reduce prefetches by writing the following bits to 72 * the value indicated: ecltr[7:6], PF_MODE = 2'b11 73 * -------------------------------------------------------- 74 */ 75 mrs x0, CORTEX_A78C_CPUECTLR_EL1 76 orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT_6 77 orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT_7 78 msr CORTEX_A78C_CPUECTLR_EL1, x0 79 isb 801: 81 ret x17 82endfunc errata_a78c_2132064_wa 83 84func check_errata_2132064 85 /* Applies to revisions r0p1 and r0p2. */ 86 mov x1, #CPU_REV(0, 1) 87 mov x2, #CPU_REV(0, 2) 88 b cpu_rev_var_range 89endfunc check_errata_2132064 90 91/* -------------------------------------------------------------------- 92 * Errata Workaround for A78C Erratum 2242638. 93 * This applies to revisions r0p1 and r0p2 of the Cortex A78C 94 * processor and is still open. 95 * x0: variant[4:7] and revision[0:3] of current cpu. 96 * Shall clobber: x0-x17 97 * -------------------------------------------------------------------- 98 */ 99func errata_a78c_2242638_wa 100 /* Compare x0 against revisions r0p1 - r0p2 */ 101 mov x17, x30 102 bl check_errata_2242638 103 cbz x0, 1f 104 105 ldr x0, =0x5 106 msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0 107 ldr x0, =0x10F600E000 108 msr CORTEX_A78C_IMP_CPUPOR_EL3, x0 109 ldr x0, =0x10FF80E000 110 msr CORTEX_A78C_IMP_CPUPMR_EL3, x0 111 ldr x0, =0x80000000003FF 112 msr CORTEX_A78C_IMP_CPUPCR_EL3, x0 113 114 isb 1151: 116 ret x17 117endfunc errata_a78c_2242638_wa 118 119func check_errata_2242638 120 /* Applies to revisions r0p1-r0p2. */ 121 mov x1, #CPU_REV(0, 1) 122 mov x2, #CPU_REV(0, 2) 123 b cpu_rev_var_range 124endfunc check_errata_2242638 125 126func check_errata_cve_2022_23960 127#if WORKAROUND_CVE_2022_23960 128 mov x0, #ERRATA_APPLIES 129#else 130 mov x0, #ERRATA_MISSING 131#endif 132 ret 133endfunc check_errata_cve_2022_23960 134 135 /* ------------------------------------------------- 136 * The CPU Ops reset function for Cortex-A78C 137 * ------------------------------------------------- 138 */ 139func cortex_a78c_reset_func 140 mov x19, x30 141 bl cpu_get_rev_var 142 mov x18, x0 143 144#if ERRATA_A78C_2132064 145 mov x0, x18 146 bl errata_a78c_2132064_wa 147#endif 148 149#if ERRATA_A78C_2242638 150 mov x0, x18 151 bl errata_a78c_2242638_wa 152#endif 153 154#if ERRATA_A78C_2395411 155 mov x0, x18 156 bl errata_a78c_2395411_wa 157#endif 158 159#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 160 /* 161 * The Cortex-A78c generic vectors are overridden to apply errata 162 * mitigation on exception entry from lower ELs. 163 */ 164 adr x0, wa_cve_vbar_cortex_a78c 165 msr vbar_el3, x0 166#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ 167 168 isb 169 ret x19 170endfunc cortex_a78c_reset_func 171 172 /* ---------------------------------------------------- 173 * HW will do the cache maintenance while powering down 174 * ---------------------------------------------------- 175 */ 176func cortex_a78c_core_pwr_dwn 177 /* --------------------------------------------------- 178 * Enable CPU power down bit in power control register 179 * --------------------------------------------------- 180 */ 181 mrs x0, CORTEX_A78C_CPUPWRCTLR_EL1 182 orr x0, x0, #CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 183 msr CORTEX_A78C_CPUPWRCTLR_EL1, x0 184 isb 185 ret 186endfunc cortex_a78c_core_pwr_dwn 187 188#if REPORT_ERRATA 189/* 190 * Errata printing function for Cortex A78C. Must follow AAPCS. 191 */ 192func cortex_a78c_errata_report 193 stp x8, x30, [sp, #-16]! 194 195 bl cpu_get_rev_var 196 mov x8, x0 197 198 /* 199 * Report all errata. The revision-variant information is passed to 200 * checking functions of each errata. 201 */ 202 report_errata ERRATA_A78C_2132064, cortex_a78c, 2132064 203 report_errata ERRATA_A78C_2242638, cortex_a78c, 2242638 204 report_errata ERRATA_A78C_2395411, cortex_a78c, 2395411 205 report_errata WORKAROUND_CVE_2022_23960, cortex_a78c, cve_2022_23960 206 207 ldp x8, x30, [sp], #16 208 ret 209endfunc cortex_a78c_errata_report 210#endif 211 212 /* --------------------------------------------- 213 * This function provides cortex_a78c specific 214 * register information for crash reporting. 215 * It needs to return with x6 pointing to 216 * a list of register names in ascii and 217 * x8 - x15 having values of registers to be 218 * reported. 219 * --------------------------------------------- 220 */ 221.section .rodata.cortex_a78c_regs, "aS" 222cortex_a78c_regs: /* The ascii list of register names to be reported */ 223 .asciz "cpuectlr_el1", "" 224 225func cortex_a78c_cpu_reg_dump 226 adr x6, cortex_a78c_regs 227 mrs x8, CORTEX_A78C_CPUECTLR_EL1 228 ret 229endfunc cortex_a78c_cpu_reg_dump 230 231declare_cpu_ops cortex_a78c, CORTEX_A78C_MIDR, \ 232 cortex_a78c_reset_func, \ 233 cortex_a78c_core_pwr_dwn 234