1/* 2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a78c.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20#if WORKAROUND_CVE_2022_23960 21 wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c 22#endif /* WORKAROUND_CVE_2022_23960 */ 23 24/* -------------------------------------------------- 25 * Errata Workaround for A78C Erratum 1827430. 26 * This applies to revision r0p0 of the Cortex A78C 27 * processor and is fixed in r0p1. 28 * x0: variant[4:7] and revision[0:3] of current cpu. 29 * Shall clobber: x0-x17 30 * -------------------------------------------------- 31 */ 32func errata_a78c_1827430_wa 33 mov x17, x30 34 bl check_errata_1827430 35 cbz x0, 1f 36 37 /* Disable allocation of splintered pages in the L2 TLB */ 38 mrs x1, CORTEX_A78C_CPUECTLR_EL1 39 orr x1, x1, CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN 40 msr CORTEX_A78C_CPUECTLR_EL1, x1 411: 42 ret x17 43endfunc errata_a78c_1827430_wa 44 45func check_errata_1827430 46 /* Applies to revision r0p0 only */ 47 mov x1, #0x00 48 b cpu_rev_var_ls 49endfunc check_errata_1827430 50 51/* -------------------------------------------------- 52 * Errata Workaround for A78C Erratum 1827440. 53 * This applies to revision r0p0 of the Cortex A78C 54 * processor and is fixed in r0p1. 55 * x0: variant[4:7] and revision[0:3] of current cpu. 56 * Shall clobber: x0-x17 57 * -------------------------------------------------- 58 */ 59func errata_a78c_1827440_wa 60 mov x17, x30 61 bl check_errata_1827440 62 cbz x0, 1f 63 64 /* Force Atomic Store to WB memory be done in L1 data cache */ 65 mrs x1, CORTEX_A78C_CPUACTLR2_EL1 66 orr x1, x1, #BIT(2) 67 msr CORTEX_A78C_CPUACTLR2_EL1, x1 681: 69 ret x17 70endfunc errata_a78c_1827440_wa 71 72func check_errata_1827440 73 /* Applies to revision r0p0 only */ 74 mov x1, #0x00 75 b cpu_rev_var_ls 76endfunc check_errata_1827440 77 78/* -------------------------------------------------- 79 * Errata Workaround for A78C Erratum 2132064. 80 * This applies to revisions r0p1 and r0p2 of A78C 81 * and is still open. 82 * Inputs: 83 * x0: variant[4:7] and revision[0:3] of current cpu. 84 * Shall clobber: x0-x17 85 * -------------------------------------------------- 86 */ 87func errata_a78c_2132064_wa 88 /* Compare x0 against revisions r0p0 - r0p1 */ 89 mov x17, x30 90 bl check_errata_2132064 91 cbz x0, 1f 92 93 /* -------------------------------------------------------- 94 * Place the data prefetcher in the most conservative mode 95 * to reduce prefetches by writing the following bits to 96 * the value indicated: ecltr[7:6], PF_MODE = 2'b11 97 * -------------------------------------------------------- 98 */ 99 mrs x0, CORTEX_A78C_CPUECTLR_EL1 100 orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT_6 101 orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT_7 102 msr CORTEX_A78C_CPUECTLR_EL1, x0 103 isb 1041: 105 ret x17 106endfunc errata_a78c_2132064_wa 107 108func check_errata_2132064 109 /* Applies to revisions r0p1 and r0p2. */ 110 mov x1, #CPU_REV(0, 1) 111 mov x2, #CPU_REV(0, 2) 112 b cpu_rev_var_range 113endfunc check_errata_2132064 114 115/* ---------------------------------------------------------- 116 * Errata Workaround for A78C Erratum 2242638. 117 * This applies to revisions r0p1 and r0p2 of the Cortex A78C 118 * processor and is still open. 119 * x0: variant[4:7] and revision[0:3] of current cpu. 120 * Shall clobber: x0-x17 121 * ---------------------------------------------------------- 122 */ 123func errata_a78c_2242638_wa 124 /* Compare x0 against revisions r0p1 - r0p2 */ 125 mov x17, x30 126 bl check_errata_2242638 127 cbz x0, 1f 128 129 ldr x0, =0x5 130 msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0 131 ldr x0, =0x10F600E000 132 msr CORTEX_A78C_IMP_CPUPOR_EL3, x0 133 ldr x0, =0x10FF80E000 134 msr CORTEX_A78C_IMP_CPUPMR_EL3, x0 135 ldr x0, =0x80000000003FF 136 msr CORTEX_A78C_IMP_CPUPCR_EL3, x0 137 138 isb 1391: 140 ret x17 141endfunc errata_a78c_2242638_wa 142 143func check_errata_2242638 144 /* Applies to revisions r0p1-r0p2. */ 145 mov x1, #CPU_REV(0, 1) 146 mov x2, #CPU_REV(0, 2) 147 b cpu_rev_var_range 148endfunc check_errata_2242638 149 150/* -------------------------------------------------- 151 * Errata Workaround for Cortex A78C Erratum 2376749. 152 * This applies to revision r0p1 and r0p2 of the A78C 153 * and is currently open. It is a Cat B erratum. 154 * Inputs: 155 * x0: variant[4:7] and revision[0:3] of current cpu. 156 * Shall clobber: x0-x4, x17 157 * -------------------------------------------------- 158 */ 159func errata_a78c_2376749_wa 160 /* Check revision */ 161 mov x17, x30 162 bl check_errata_2376749 163 cbz x0, 1f 164 /* Set CPUACTLR2_EL1[0] to 1. */ 165 mrs x1, CORTEX_A78C_CPUACTLR2_EL1 166 orr x1, x1, #CORTEX_A78C_CPUACTLR2_EL1_BIT_0 167 msr CORTEX_A78C_CPUACTLR2_EL1, x1 1681: 169 ret x17 170endfunc errata_a78c_2376749_wa 171 172func check_errata_2376749 173 /* Applies to r0p1 and r0p2*/ 174 mov x1, #0x01 175 mov x2, #0x02 176 b cpu_rev_var_range 177endfunc check_errata_2376749 178 179/* -------------------------------------------------- 180 * Errata Workaround for Cortex A78C Erratum 2395411. 181 * This applies to revision r0p1 and r0p2 of the A78C 182 * and is currently open. It is a Cat B erratum. 183 * Inputs: 184 * x0: variant[4:7] and revision[0:3] of current cpu. 185 * Shall clobber: x0-x4, x17 186 * -------------------------------------------------- 187 */ 188func errata_a78c_2395411_wa 189 /* Check revision. */ 190 mov x17, x30 191 bl check_errata_2395411 192 cbz x0, 1f 193 194 /* Set CPUACTRL2_EL1[40] to 1. */ 195 mrs x1, CORTEX_A78C_CPUACTLR2_EL1 196 orr x1, x1, #CORTEX_A78C_CPUACTLR2_EL1_BIT_40 197 msr CORTEX_A78C_CPUACTLR2_EL1, x1 1981: 199 ret x17 200endfunc errata_a78c_2395411_wa 201 202func check_errata_2395411 203 /* Applies to r0p1 and r0p2 */ 204 mov x1, #0x01 205 mov x2, #0x02 206 b cpu_rev_var_range 207endfunc check_errata_2395411 208 209/* ---------------------------------------------------------------- 210 * Errata Workaround for A78C Erratum 2772121. 211 * This applies to revisions r0p0, r0p1 and r0p2 of the Cortex A78C 212 * processor and is still open. 213 * x0: variant[4:7] and revision[0:3] of current cpu. 214 * Shall clobber: x0-x17 215 * ---------------------------------------------------------------- 216 */ 217func errata_a78c_2772121_wa 218 mov x17, x30 219 bl check_errata_2772121 220 cbz x0, 1f 221 222 /* dsb before isb of power down sequence */ 223 dsb sy 2241: 225 ret x17 226endfunc errata_a78c_2772121_wa 227 228func check_errata_2772121 229 /* Applies to all revisions <= r0p2 */ 230 mov x1, #0x02 231 b cpu_rev_var_ls 232endfunc check_errata_2772121 233 234/* -------------------------------------------------- 235 * Errata Workaround for Cortex A78C Errata 2779484. 236 * This applies to revisions r0p1 and r0p2. 237 * It is still open. 238 * x0: variant[4:7] and revision[0:3] of current cpu. 239 * Shall clobber: x0-x1, x17 240 * -------------------------------------------------- 241 */ 242func errata_a78c_2779484_wa 243 /* Check revision. */ 244 mov x17, x30 245 bl check_errata_2779484 246 cbz x0, 1f 247 248 /* Apply the workaround */ 249 mrs x1, CORTEX_A78C_ACTLR3_EL1 250 orr x1, x1, #BIT(47) 251 msr CORTEX_A78C_ACTLR3_EL1, x1 252 2531: 254 ret x17 255endfunc errata_a78c_2779484_wa 256 257func check_errata_2779484 258 /* Applies to r0p1 and r0p2*/ 259 mov x1, #0x01 260 mov x2, #0x02 261 b cpu_rev_var_range 262endfunc check_errata_2779484 263 264func check_errata_cve_2022_23960 265#if WORKAROUND_CVE_2022_23960 266 mov x0, #ERRATA_APPLIES 267#else 268 mov x0, #ERRATA_MISSING 269#endif 270 ret 271endfunc check_errata_cve_2022_23960 272 273 /* ------------------------------------------------- 274 * The CPU Ops reset function for Cortex-A78C 275 * ------------------------------------------------- 276 */ 277func cortex_a78c_reset_func 278 mov x19, x30 279 bl cpu_get_rev_var 280 mov x18, x0 281 282#if ERRATA_A78C_1827430 283 mov x0, x18 284 bl errata_a78c_1827430_wa 285#endif 286 287#if ERRATA_A78C_1827440 288 mov x0, x18 289 bl errata_a78c_1827440_wa 290#endif 291 292#if ERRATA_A78C_2132064 293 mov x0, x18 294 bl errata_a78c_2132064_wa 295#endif 296 297#if ERRATA_A78C_2242638 298 mov x0, x18 299 bl errata_a78c_2242638_wa 300#endif 301 302#if ERRATA_A78C_2376749 303 mov x0, x18 304 bl errata_a78c_2376749_wa 305#endif 306 307#if ERRATA_A78C_2395411 308 mov x0, x18 309 bl errata_a78c_2395411_wa 310#endif 311 312#if ERRATA_A78C_2779484 313 mov x0, x18 314 bl errata_a78c_2779484_wa 315#endif 316 317#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 318 /* 319 * The Cortex-A78c generic vectors are overridden to apply errata 320 * mitigation on exception entry from lower ELs. 321 */ 322 adr x0, wa_cve_vbar_cortex_a78c 323 msr vbar_el3, x0 324#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ 325 326 isb 327 ret x19 328endfunc cortex_a78c_reset_func 329 330 /* ---------------------------------------------------- 331 * HW will do the cache maintenance while powering down 332 * ---------------------------------------------------- 333 */ 334func cortex_a78c_core_pwr_dwn 335 /* --------------------------------------------------- 336 * Enable CPU power down bit in power control register 337 * --------------------------------------------------- 338 */ 339 mrs x0, CORTEX_A78C_CPUPWRCTLR_EL1 340 orr x0, x0, #CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 341 msr CORTEX_A78C_CPUPWRCTLR_EL1, x0 342#if ERRATA_A78C_2772121 343 mov x15, x30 344 bl cpu_get_rev_var 345 bl errata_a78c_2772121_wa 346 mov x30, x15 347#endif /* ERRATA_A78C_2772121 */ 348 isb 349 ret 350endfunc cortex_a78c_core_pwr_dwn 351 352#if REPORT_ERRATA 353/* 354 * Errata printing function for Cortex A78C. Must follow AAPCS. 355 */ 356func cortex_a78c_errata_report 357 stp x8, x30, [sp, #-16]! 358 359 bl cpu_get_rev_var 360 mov x8, x0 361 362 /* 363 * Report all errata. The revision-variant information is passed to 364 * checking functions of each errata. 365 */ 366 report_errata ERRATA_A78C_1827430, cortex_a78c, 1827430 367 report_errata ERRATA_A78C_1827440, cortex_a78c, 1827440 368 report_errata ERRATA_A78C_2132064, cortex_a78c, 2132064 369 report_errata ERRATA_A78C_2242638, cortex_a78c, 2242638 370 report_errata ERRATA_A78C_2376749, cortex_a78c, 2376749 371 report_errata ERRATA_A78C_2395411, cortex_a78c, 2395411 372 report_errata ERRATA_A78C_2772121, cortex_a78c, 2772121 373 report_errata ERRATA_A78C_2779484, cortex_a78c, 2779484 374 report_errata WORKAROUND_CVE_2022_23960, cortex_a78c, cve_2022_23960 375 376 ldp x8, x30, [sp], #16 377 ret 378endfunc cortex_a78c_errata_report 379#endif 380 381 /* --------------------------------------------- 382 * This function provides cortex_a78c specific 383 * register information for crash reporting. 384 * It needs to return with x6 pointing to 385 * a list of register names in ascii and 386 * x8 - x15 having values of registers to be 387 * reported. 388 * --------------------------------------------- 389 */ 390.section .rodata.cortex_a78c_regs, "aS" 391cortex_a78c_regs: /* The ascii list of register names to be reported */ 392 .asciz "cpuectlr_el1", "" 393 394func cortex_a78c_cpu_reg_dump 395 adr x6, cortex_a78c_regs 396 mrs x8, CORTEX_A78C_CPUECTLR_EL1 397 ret 398endfunc cortex_a78c_cpu_reg_dump 399 400declare_cpu_ops cortex_a78c, CORTEX_A78C_MIDR, \ 401 cortex_a78c_reset_func, \ 402 cortex_a78c_core_pwr_dwn 403