1/* 2 * Copyright (c) 2019-2020, ARM Limited. All rights reserved. 3 * Copyright (c) 2021, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8#include <arch.h> 9#include <asm_macros.S> 10#include <common/bl_common.h> 11#include <cortex_a78_ae.h> 12#include <cpu_macros.S> 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "cortex_a78_ae must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* -------------------------------------------------- 21 * Errata Workaround for A78 AE Erratum 1951502. 22 * This applies to revisions r0p0 and r0p1 of A78 AE. 23 * Inputs: 24 * x0: variant[4:7] and revision[0:3] of current cpu. 25 * Shall clobber: x0-x17 26 * -------------------------------------------------- 27 */ 28func errata_a78_ae_1951502_wa 29 /* Compare x0 against revisions r0p0 - r0p1 */ 30 mov x17, x30 31 bl check_errata_1951502 32 cbz x0, 1f 33 34 msr S3_6_c15_c8_0, xzr 35 ldr x0, =0x10E3900002 36 msr S3_6_c15_c8_2, x0 37 ldr x0, =0x10FFF00083 38 msr S3_6_c15_c8_3, x0 39 ldr x0, =0x2001003FF 40 msr S3_6_c15_c8_1, x0 41 42 mov x0, #1 43 msr S3_6_c15_c8_0, x0 44 ldr x0, =0x10E3800082 45 msr S3_6_c15_c8_2, x0 46 ldr x0, =0x10FFF00083 47 msr S3_6_c15_c8_3, x0 48 ldr x0, =0x2001003FF 49 msr S3_6_c15_c8_1, x0 50 51 mov x0, #2 52 msr S3_6_c15_c8_0, x0 53 ldr x0, =0x10E3800200 54 msr S3_6_c15_c8_2, x0 55 ldr x0, =0x10FFF003E0 56 msr S3_6_c15_c8_3, x0 57 ldr x0, =0x2001003FF 58 msr S3_6_c15_c8_1, x0 59 60 isb 611: 62 ret x17 63endfunc errata_a78_ae_1951502_wa 64 65func check_errata_1951502 66 /* Applies to revisions r0p0 and r0p1. */ 67 mov x1, #CPU_REV(0, 0) 68 mov x2, #CPU_REV(0, 1) 69 b cpu_rev_var_range 70endfunc check_errata_1951502 71 72 /* ------------------------------------------------- 73 * The CPU Ops reset function for Cortex-A78-AE 74 * ------------------------------------------------- 75 */ 76func cortex_a78_ae_reset_func 77 mov x19, x30 78 bl cpu_get_rev_var 79 mov x18, x0 80 81#if ERRATA_A78_AE_1951502 82 mov x0, x18 83 bl errata_a78_ae_1951502_wa 84#endif 85 86#if ENABLE_AMU 87 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 88 mrs x0, actlr_el3 89 bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT 90 msr actlr_el3, x0 91 92 /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */ 93 mrs x0, actlr_el2 94 bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT 95 msr actlr_el2, x0 96 97 /* Enable group0 counters */ 98 mov x0, #CORTEX_A78_AMU_GROUP0_MASK 99 msr CPUAMCNTENSET0_EL0, x0 100 101 /* Enable group1 counters */ 102 mov x0, #CORTEX_A78_AMU_GROUP1_MASK 103 msr CPUAMCNTENSET1_EL0, x0 104#endif 105 106 isb 107 108 ret x19 109endfunc cortex_a78_ae_reset_func 110 111 /* ------------------------------------------------------- 112 * HW will do the cache maintenance while powering down 113 * ------------------------------------------------------- 114 */ 115func cortex_a78_ae_core_pwr_dwn 116 /* ------------------------------------------------------- 117 * Enable CPU power down bit in power control register 118 * ------------------------------------------------------- 119 */ 120 mrs x0, CORTEX_A78_CPUPWRCTLR_EL1 121 orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 122 msr CORTEX_A78_CPUPWRCTLR_EL1, x0 123 isb 124 ret 125endfunc cortex_a78_ae_core_pwr_dwn 126 127 /* 128 * Errata printing function for cortex_a78_ae. Must follow AAPCS. 129 */ 130#if REPORT_ERRATA 131func cortex_a78_ae_errata_report 132 stp x8, x30, [sp, #-16]! 133 134 bl cpu_get_rev_var 135 mov x8, x0 136 137 /* 138 * Report all errata. The revision-variant information is passed to 139 * checking functions of each errata. 140 */ 141 report_errata ERRATA_A78_AE_1951502, cortex_a78_ae, 1951502 142 143 ldp x8, x30, [sp], #16 144 ret 145endfunc cortex_a78_ae_errata_report 146#endif 147 148 /* ------------------------------------------------------- 149 * This function provides cortex_a78_ae specific 150 * register information for crash reporting. 151 * It needs to return with x6 pointing to 152 * a list of register names in ascii and 153 * x8 - x15 having values of registers to be 154 * reported. 155 * ------------------------------------------------------- 156 */ 157.section .rodata.cortex_a78_ae_regs, "aS" 158cortex_a78_ae_regs: /* The ascii list of register names to be reported */ 159 .asciz "cpuectlr_el1", "" 160 161func cortex_a78_ae_cpu_reg_dump 162 adr x6, cortex_a78_ae_regs 163 mrs x8, CORTEX_A78_CPUECTLR_EL1 164 ret 165endfunc cortex_a78_ae_cpu_reg_dump 166 167declare_cpu_ops cortex_a78_ae, CORTEX_A78_AE_MIDR, \ 168 cortex_a78_ae_reset_func, \ 169 cortex_a78_ae_core_pwr_dwn 170