1/* 2 * Copyright (c) 2019-2021, ARM Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a78.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "cortex_a78 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19 20/* -------------------------------------------------- 21 * Errata Workaround for A78 Erratum 1688305. 22 * This applies to revision r0p0 and r1p0 of A78. 23 * Inputs: 24 * x0: variant[4:7] and revision[0:3] of current cpu. 25 * Shall clobber: x0-x17 26 * -------------------------------------------------- 27 */ 28func errata_a78_1688305_wa 29 /* Compare x0 against revision r1p0 */ 30 mov x17, x30 31 bl check_errata_1688305 32 cbz x0, 1f 33 mrs x1, CORTEX_A78_ACTLR2_EL1 34 orr x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_1 35 msr CORTEX_A78_ACTLR2_EL1, x1 36 isb 371: 38 ret x17 39endfunc errata_a78_1688305_wa 40 41func check_errata_1688305 42 /* Applies to r0p0 and r1p0 */ 43 mov x1, #0x10 44 b cpu_rev_var_ls 45endfunc check_errata_1688305 46 47/* -------------------------------------------------- 48 * Errata Workaround for Cortex A78 Errata #1941498. 49 * This applies to revisions r0p0, r1p0, and r1p1. 50 * x0: variant[4:7] and revision[0:3] of current cpu. 51 * Shall clobber: x0-x17 52 * -------------------------------------------------- 53 */ 54func errata_a78_1941498_wa 55 /* Compare x0 against revision <= r1p1 */ 56 mov x17, x30 57 bl check_errata_1941498 58 cbz x0, 1f 59 60 /* Set bit 8 in ECTLR_EL1 */ 61 mrs x1, CORTEX_A78_CPUECTLR_EL1 62 orr x1, x1, #CORTEX_A78_CPUECTLR_EL1_BIT_8 63 msr CORTEX_A78_CPUECTLR_EL1, x1 64 isb 651: 66 ret x17 67endfunc errata_a78_1941498_wa 68 69func check_errata_1941498 70 /* Check for revision <= r1p1, might need to be updated later. */ 71 mov x1, #0x11 72 b cpu_rev_var_ls 73endfunc check_errata_1941498 74 75/* -------------------------------------------------- 76 * Errata Workaround for A78 Erratum 1951500. 77 * This applies to revisions r1p0 and r1p1 of A78. 78 * The issue also exists in r0p0 but there is no fix 79 * in that revision. 80 * Inputs: 81 * x0: variant[4:7] and revision[0:3] of current cpu. 82 * Shall clobber: x0-x17 83 * -------------------------------------------------- 84 */ 85func errata_a78_1951500_wa 86 /* Compare x0 against revisions r1p0 - r1p1 */ 87 mov x17, x30 88 bl check_errata_1951500 89 cbz x0, 1f 90 91 msr S3_6_c15_c8_0, xzr 92 ldr x0, =0x10E3900002 93 msr S3_6_c15_c8_2, x0 94 ldr x0, =0x10FFF00083 95 msr S3_6_c15_c8_3, x0 96 ldr x0, =0x2001003FF 97 msr S3_6_c15_c8_1, x0 98 99 mov x0, #1 100 msr S3_6_c15_c8_0, x0 101 ldr x0, =0x10E3800082 102 msr S3_6_c15_c8_2, x0 103 ldr x0, =0x10FFF00083 104 msr S3_6_c15_c8_3, x0 105 ldr x0, =0x2001003FF 106 msr S3_6_c15_c8_1, x0 107 108 mov x0, #2 109 msr S3_6_c15_c8_0, x0 110 ldr x0, =0x10E3800200 111 msr S3_6_c15_c8_2, x0 112 ldr x0, =0x10FFF003E0 113 msr S3_6_c15_c8_3, x0 114 ldr x0, =0x2001003FF 115 msr S3_6_c15_c8_1, x0 116 117 isb 1181: 119 ret x17 120endfunc errata_a78_1951500_wa 121 122func check_errata_1951500 123 /* Applies to revisions r1p0 and r1p1. */ 124 mov x1, #CPU_REV(1, 0) 125 mov x2, #CPU_REV(1, 1) 126 b cpu_rev_var_range 127endfunc check_errata_1951500 128 129/* -------------------------------------------------- 130 * Errata Workaround for Cortex A78 Errata #1821534. 131 * This applies to revisions r0p0 and r1p0. 132 * x0: variant[4:7] and revision[0:3] of current cpu. 133 * Shall clobber: x0-x17 134 * -------------------------------------------------- 135 */ 136func errata_a78_1821534_wa 137 /* Check revision. */ 138 mov x17, x30 139 bl check_errata_1821534 140 cbz x0, 1f 141 142 /* Set bit 2 in ACTLR2_EL1 */ 143 mrs x1, CORTEX_A78_ACTLR2_EL1 144 orr x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_2 145 msr CORTEX_A78_ACTLR2_EL1, x1 146 isb 1471: 148 ret x17 149endfunc errata_a78_1821534_wa 150 151func check_errata_1821534 152 /* Applies to r0p0 and r1p0 */ 153 mov x1, #0x10 154 b cpu_rev_var_ls 155endfunc check_errata_1821534 156 157 /* ------------------------------------------------- 158 * The CPU Ops reset function for Cortex-A78 159 * ------------------------------------------------- 160 */ 161func cortex_a78_reset_func 162 mov x19, x30 163 bl cpu_get_rev_var 164 mov x18, x0 165 166#if ERRATA_A78_1688305 167 mov x0, x18 168 bl errata_a78_1688305_wa 169#endif 170 171#if ERRATA_A78_1941498 172 mov x0, x18 173 bl errata_a78_1941498_wa 174#endif 175 176#if ERRATA_A78_1951500 177 mov x0, x18 178 bl errata_a78_1951500_wa 179#endif 180 181#if ERRATA_A78_1821534 182 mov x0, x18 183 bl errata_a78_1821534_wa 184#endif 185 186#if ENABLE_AMU 187 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 188 mrs x0, actlr_el3 189 bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT 190 msr actlr_el3, x0 191 192 /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */ 193 mrs x0, actlr_el2 194 bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT 195 msr actlr_el2, x0 196 197 /* Enable group0 counters */ 198 mov x0, #CORTEX_A78_AMU_GROUP0_MASK 199 msr CPUAMCNTENSET0_EL0, x0 200 201 /* Enable group1 counters */ 202 mov x0, #CORTEX_A78_AMU_GROUP1_MASK 203 msr CPUAMCNTENSET1_EL0, x0 204#endif 205 206 isb 207 ret x19 208endfunc cortex_a78_reset_func 209 210 /* --------------------------------------------- 211 * HW will do the cache maintenance while powering down 212 * --------------------------------------------- 213 */ 214func cortex_a78_core_pwr_dwn 215 /* --------------------------------------------- 216 * Enable CPU power down bit in power control register 217 * --------------------------------------------- 218 */ 219 mrs x0, CORTEX_A78_CPUPWRCTLR_EL1 220 orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 221 msr CORTEX_A78_CPUPWRCTLR_EL1, x0 222 isb 223 ret 224endfunc cortex_a78_core_pwr_dwn 225 226 /* 227 * Errata printing function for cortex_a78. Must follow AAPCS. 228 */ 229#if REPORT_ERRATA 230func cortex_a78_errata_report 231 stp x8, x30, [sp, #-16]! 232 233 bl cpu_get_rev_var 234 mov x8, x0 235 236 /* 237 * Report all errata. The revision-variant information is passed to 238 * checking functions of each errata. 239 */ 240 report_errata ERRATA_A78_1688305, cortex_a78, 1688305 241 report_errata ERRATA_A78_1941498, cortex_a78, 1941498 242 report_errata ERRATA_A78_1951500, cortex_a78, 1951500 243 report_errata ERRATA_A78_1821534, cortex_a78, 1821534 244 245 ldp x8, x30, [sp], #16 246 ret 247endfunc cortex_a78_errata_report 248#endif 249 250 /* --------------------------------------------- 251 * This function provides cortex_a78 specific 252 * register information for crash reporting. 253 * It needs to return with x6 pointing to 254 * a list of register names in ascii and 255 * x8 - x15 having values of registers to be 256 * reported. 257 * --------------------------------------------- 258 */ 259.section .rodata.cortex_a78_regs, "aS" 260cortex_a78_regs: /* The ascii list of register names to be reported */ 261 .asciz "cpuectlr_el1", "" 262 263func cortex_a78_cpu_reg_dump 264 adr x6, cortex_a78_regs 265 mrs x8, CORTEX_A78_CPUECTLR_EL1 266 ret 267endfunc cortex_a78_cpu_reg_dump 268 269declare_cpu_ops cortex_a78, CORTEX_A78_MIDR, \ 270 cortex_a78_reset_func, \ 271 cortex_a78_core_pwr_dwn 272