1/* 2 * Copyright (c) 2019-2022, ARM Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a78.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "cortex_a78 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20#if WORKAROUND_CVE_2022_23960 21 wa_cve_2022_23960_bhb_vector_table CORTEX_A78_BHB_LOOP_COUNT, cortex_a78 22#endif /* WORKAROUND_CVE_2022_23960 */ 23 24/* -------------------------------------------------- 25 * Errata Workaround for A78 Erratum 1688305. 26 * This applies to revision r0p0 and r1p0 of A78. 27 * Inputs: 28 * x0: variant[4:7] and revision[0:3] of current cpu. 29 * Shall clobber: x0-x17 30 * -------------------------------------------------- 31 */ 32func errata_a78_1688305_wa 33 /* Compare x0 against revision r1p0 */ 34 mov x17, x30 35 bl check_errata_1688305 36 cbz x0, 1f 37 mrs x1, CORTEX_A78_ACTLR2_EL1 38 orr x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_1 39 msr CORTEX_A78_ACTLR2_EL1, x1 40 isb 411: 42 ret x17 43endfunc errata_a78_1688305_wa 44 45func check_errata_1688305 46 /* Applies to r0p0 and r1p0 */ 47 mov x1, #0x10 48 b cpu_rev_var_ls 49endfunc check_errata_1688305 50 51/* -------------------------------------------------- 52 * Errata Workaround for Cortex A78 Errata #1941498. 53 * This applies to revisions r0p0, r1p0, and r1p1. 54 * x0: variant[4:7] and revision[0:3] of current cpu. 55 * Shall clobber: x0-x17 56 * -------------------------------------------------- 57 */ 58func errata_a78_1941498_wa 59 /* Compare x0 against revision <= r1p1 */ 60 mov x17, x30 61 bl check_errata_1941498 62 cbz x0, 1f 63 64 /* Set bit 8 in ECTLR_EL1 */ 65 mrs x1, CORTEX_A78_CPUECTLR_EL1 66 orr x1, x1, #CORTEX_A78_CPUECTLR_EL1_BIT_8 67 msr CORTEX_A78_CPUECTLR_EL1, x1 68 isb 691: 70 ret x17 71endfunc errata_a78_1941498_wa 72 73func check_errata_1941498 74 /* Check for revision <= r1p1, might need to be updated later. */ 75 mov x1, #0x11 76 b cpu_rev_var_ls 77endfunc check_errata_1941498 78 79/* -------------------------------------------------- 80 * Errata Workaround for A78 Erratum 1951500. 81 * This applies to revisions r1p0 and r1p1 of A78. 82 * The issue also exists in r0p0 but there is no fix 83 * in that revision. 84 * Inputs: 85 * x0: variant[4:7] and revision[0:3] of current cpu. 86 * Shall clobber: x0-x17 87 * -------------------------------------------------- 88 */ 89func errata_a78_1951500_wa 90 /* Compare x0 against revisions r1p0 - r1p1 */ 91 mov x17, x30 92 bl check_errata_1951500 93 cbz x0, 1f 94 95 msr S3_6_c15_c8_0, xzr 96 ldr x0, =0x10E3900002 97 msr S3_6_c15_c8_2, x0 98 ldr x0, =0x10FFF00083 99 msr S3_6_c15_c8_3, x0 100 ldr x0, =0x2001003FF 101 msr S3_6_c15_c8_1, x0 102 103 mov x0, #1 104 msr S3_6_c15_c8_0, x0 105 ldr x0, =0x10E3800082 106 msr S3_6_c15_c8_2, x0 107 ldr x0, =0x10FFF00083 108 msr S3_6_c15_c8_3, x0 109 ldr x0, =0x2001003FF 110 msr S3_6_c15_c8_1, x0 111 112 mov x0, #2 113 msr S3_6_c15_c8_0, x0 114 ldr x0, =0x10E3800200 115 msr S3_6_c15_c8_2, x0 116 ldr x0, =0x10FFF003E0 117 msr S3_6_c15_c8_3, x0 118 ldr x0, =0x2001003FF 119 msr S3_6_c15_c8_1, x0 120 121 isb 1221: 123 ret x17 124endfunc errata_a78_1951500_wa 125 126func check_errata_1951500 127 /* Applies to revisions r1p0 and r1p1. */ 128 mov x1, #CPU_REV(1, 0) 129 mov x2, #CPU_REV(1, 1) 130 b cpu_rev_var_range 131endfunc check_errata_1951500 132 133/* -------------------------------------------------- 134 * Errata Workaround for Cortex A78 Errata #1821534. 135 * This applies to revisions r0p0 and r1p0. 136 * x0: variant[4:7] and revision[0:3] of current cpu. 137 * Shall clobber: x0-x17 138 * -------------------------------------------------- 139 */ 140func errata_a78_1821534_wa 141 /* Check revision. */ 142 mov x17, x30 143 bl check_errata_1821534 144 cbz x0, 1f 145 146 /* Set bit 2 in ACTLR2_EL1 */ 147 mrs x1, CORTEX_A78_ACTLR2_EL1 148 orr x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_2 149 msr CORTEX_A78_ACTLR2_EL1, x1 150 isb 1511: 152 ret x17 153endfunc errata_a78_1821534_wa 154 155func check_errata_1821534 156 /* Applies to r0p0 and r1p0 */ 157 mov x1, #0x10 158 b cpu_rev_var_ls 159endfunc check_errata_1821534 160 161/* -------------------------------------------------- 162 * Errata Workaround for Cortex A78 Errata 1952683. 163 * This applies to revision r0p0. 164 * x0: variant[4:7] and revision[0:3] of current cpu. 165 * Shall clobber: x0-x17 166 * -------------------------------------------------- 167 */ 168func errata_a78_1952683_wa 169 /* Check revision. */ 170 mov x17, x30 171 bl check_errata_1952683 172 cbz x0, 1f 173 174 ldr x0,=0x5 175 msr S3_6_c15_c8_0,x0 176 ldr x0,=0xEEE10A10 177 msr S3_6_c15_c8_2,x0 178 ldr x0,=0xFFEF0FFF 179 msr S3_6_c15_c8_3,x0 180 ldr x0,=0x0010F000 181 msr S3_6_c15_c8_4,x0 182 ldr x0,=0x0010F000 183 msr S3_6_c15_c8_5,x0 184 ldr x0,=0x40000080023ff 185 msr S3_6_c15_c8_1,x0 186 ldr x0,=0x6 187 msr S3_6_c15_c8_0,x0 188 ldr x0,=0xEE640F34 189 msr S3_6_c15_c8_2,x0 190 ldr x0,=0xFFEF0FFF 191 msr S3_6_c15_c8_3,x0 192 ldr x0,=0x40000080023ff 193 msr S3_6_c15_c8_1,x0 194 isb 1951: 196 ret x17 197endfunc errata_a78_1952683_wa 198 199func check_errata_1952683 200 /* Applies to r0p0 only */ 201 mov x1, #0x00 202 b cpu_rev_var_ls 203endfunc check_errata_1952683 204 205/* -------------------------------------------------- 206 * Errata Workaround for Cortex A78 Errata 2132060. 207 * This applies to revisions r0p0, r1p0, r1p1, and r1p2. 208 * It is still open. 209 * x0: variant[4:7] and revision[0:3] of current cpu. 210 * Shall clobber: x0-x1, x17 211 * -------------------------------------------------- 212 */ 213func errata_a78_2132060_wa 214 /* Check revision. */ 215 mov x17, x30 216 bl check_errata_2132060 217 cbz x0, 1f 218 219 /* Apply the workaround. */ 220 mrs x1, CORTEX_A78_CPUECTLR_EL1 221 mov x0, #CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV 222 bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH 223 msr CORTEX_A78_CPUECTLR_EL1, x1 2241: 225 ret x17 226endfunc errata_a78_2132060_wa 227 228func check_errata_2132060 229 /* Applies to r0p0, r0p1, r1p1, and r1p2 */ 230 mov x1, #0x12 231 b cpu_rev_var_ls 232endfunc check_errata_2132060 233 234/* -------------------------------------------------------------------- 235 * Errata Workaround for A78 Erratum 2242635. 236 * This applies to revisions r1p0, r1p1, and r1p2 of the Cortex A78 237 * processor and is still open. 238 * The issue also exists in r0p0 but there is no fix in that revision. 239 * x0: variant[4:7] and revision[0:3] of current cpu. 240 * Shall clobber: x0-x17 241 * -------------------------------------------------------------------- 242 */ 243func errata_a78_2242635_wa 244 /* Compare x0 against revisions r1p0 - r1p2 */ 245 mov x17, x30 246 bl check_errata_2242635 247 cbz x0, 1f 248 249 ldr x0, =0x5 250 msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */ 251 ldr x0, =0x10F600E000 252 msr S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */ 253 ldr x0, =0x10FF80E000 254 msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */ 255 ldr x0, =0x80000000003FF 256 msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */ 257 258 isb 2591: 260 ret x17 261endfunc errata_a78_2242635_wa 262 263func check_errata_2242635 264 /* Applies to revisions r1p0 through r1p2. */ 265 mov x1, #CPU_REV(1, 0) 266 mov x2, #CPU_REV(1, 2) 267 b cpu_rev_var_range 268endfunc check_errata_2242635 269 270/* -------------------------------------------------- 271 * Errata Workaround for Cortex A78 Errata 2376745. 272 * This applies to revisions r0p0, r1p0, r1p1, and r1p2. 273 * It is still open. 274 * x0: variant[4:7] and revision[0:3] of current cpu. 275 * Shall clobber: x0-x1, x17 276 * -------------------------------------------------- 277 */ 278func errata_a78_2376745_wa 279 /* Check revision. */ 280 mov x17, x30 281 bl check_errata_2376745 282 cbz x0, 1f 283 284 /* Apply the workaround. */ 285 mrs x1, CORTEX_A78_ACTLR2_EL1 286 orr x1, x1, #BIT(0) 287 msr CORTEX_A78_ACTLR2_EL1, x1 2881: 289 ret x17 290endfunc errata_a78_2376745_wa 291 292func check_errata_2376745 293 /* Applies to r0p0, r0p1, r1p1, and r1p2 */ 294 mov x1, #CPU_REV(1, 2) 295 b cpu_rev_var_ls 296endfunc check_errata_2376745 297 298func check_errata_cve_2022_23960 299#if WORKAROUND_CVE_2022_23960 300 mov x0, #ERRATA_APPLIES 301#else 302 mov x0, #ERRATA_MISSING 303#endif 304 ret 305endfunc check_errata_cve_2022_23960 306 307 /* ------------------------------------------------- 308 * The CPU Ops reset function for Cortex-A78 309 * ------------------------------------------------- 310 */ 311func cortex_a78_reset_func 312 mov x19, x30 313 bl cpu_get_rev_var 314 mov x18, x0 315 316#if ERRATA_A78_1688305 317 mov x0, x18 318 bl errata_a78_1688305_wa 319#endif 320 321#if ERRATA_A78_1941498 322 mov x0, x18 323 bl errata_a78_1941498_wa 324#endif 325 326#if ERRATA_A78_1951500 327 mov x0, x18 328 bl errata_a78_1951500_wa 329#endif 330 331#if ERRATA_A78_1821534 332 mov x0, x18 333 bl errata_a78_1821534_wa 334#endif 335 336#if ERRATA_A78_1952683 337 mov x0, x18 338 bl errata_a78_1952683_wa 339#endif 340 341#if ERRATA_A78_2132060 342 mov x0, x18 343 bl errata_a78_2132060_wa 344#endif 345 346#if ERRATA_A78_2242635 347 mov x0, x18 348 bl errata_a78_2242635_wa 349#endif 350 351#if ERRATA_A78_2376745 352 mov x0, x18 353 bl errata_a78_2376745_wa 354#endif 355 356#if ENABLE_AMU 357 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 358 mrs x0, actlr_el3 359 bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT 360 msr actlr_el3, x0 361 362 /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */ 363 mrs x0, actlr_el2 364 bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT 365 msr actlr_el2, x0 366 367 /* Enable group0 counters */ 368 mov x0, #CORTEX_A78_AMU_GROUP0_MASK 369 msr CPUAMCNTENSET0_EL0, x0 370 371 /* Enable group1 counters */ 372 mov x0, #CORTEX_A78_AMU_GROUP1_MASK 373 msr CPUAMCNTENSET1_EL0, x0 374#endif 375 376#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 377 /* 378 * The Cortex-A78 generic vectors are overridden to apply errata 379 * mitigation on exception entry from lower ELs. 380 */ 381 adr x0, wa_cve_vbar_cortex_a78 382 msr vbar_el3, x0 383#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ 384 385 isb 386 ret x19 387endfunc cortex_a78_reset_func 388 389 /* --------------------------------------------- 390 * HW will do the cache maintenance while powering down 391 * --------------------------------------------- 392 */ 393func cortex_a78_core_pwr_dwn 394 /* --------------------------------------------- 395 * Enable CPU power down bit in power control register 396 * --------------------------------------------- 397 */ 398 mrs x0, CORTEX_A78_CPUPWRCTLR_EL1 399 orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 400 msr CORTEX_A78_CPUPWRCTLR_EL1, x0 401 isb 402 ret 403endfunc cortex_a78_core_pwr_dwn 404 405 /* 406 * Errata printing function for cortex_a78. Must follow AAPCS. 407 */ 408#if REPORT_ERRATA 409func cortex_a78_errata_report 410 stp x8, x30, [sp, #-16]! 411 412 bl cpu_get_rev_var 413 mov x8, x0 414 415 /* 416 * Report all errata. The revision-variant information is passed to 417 * checking functions of each errata. 418 */ 419 report_errata ERRATA_A78_1688305, cortex_a78, 1688305 420 report_errata ERRATA_A78_1941498, cortex_a78, 1941498 421 report_errata ERRATA_A78_1951500, cortex_a78, 1951500 422 report_errata ERRATA_A78_1821534, cortex_a78, 1821534 423 report_errata ERRATA_A78_1952683, cortex_a78, 1952683 424 report_errata ERRATA_A78_2132060, cortex_a78, 2132060 425 report_errata ERRATA_A78_2242635, cortex_a78, 2242635 426 report_errata ERRATA_A78_2376745, cortex_a78, 2376745 427 report_errata WORKAROUND_CVE_2022_23960, cortex_a78, cve_2022_23960 428 429 ldp x8, x30, [sp], #16 430 ret 431endfunc cortex_a78_errata_report 432#endif 433 434 /* --------------------------------------------- 435 * This function provides cortex_a78 specific 436 * register information for crash reporting. 437 * It needs to return with x6 pointing to 438 * a list of register names in ascii and 439 * x8 - x15 having values of registers to be 440 * reported. 441 * --------------------------------------------- 442 */ 443.section .rodata.cortex_a78_regs, "aS" 444cortex_a78_regs: /* The ascii list of register names to be reported */ 445 .asciz "cpuectlr_el1", "" 446 447func cortex_a78_cpu_reg_dump 448 adr x6, cortex_a78_regs 449 mrs x8, CORTEX_A78_CPUECTLR_EL1 450 ret 451endfunc cortex_a78_cpu_reg_dump 452 453declare_cpu_ops cortex_a78, CORTEX_A78_MIDR, \ 454 cortex_a78_reset_func, \ 455 cortex_a78_core_pwr_dwn 456