1/* 2 * Copyright (c) 2019-2020, ARM Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a78.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "cortex_a78 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19 20/* -------------------------------------------------- 21 * Errata Workaround for A78 Erratum 1688305. 22 * This applies to revision r0p0 and r1p0 of A78. 23 * Inputs: 24 * x0: variant[4:7] and revision[0:3] of current cpu. 25 * Shall clobber: x0-x17 26 * -------------------------------------------------- 27 */ 28func errata_a78_1688305_wa 29 /* Compare x0 against revision r1p0 */ 30 mov x17, x30 31 bl check_errata_1688305 32 cbz x0, 1f 33 mrs x1, CORTEX_A78_ACTLR2_EL1 34 orr x1, x1, CORTEX_A78_ACTLR2_EL1_BIT_1 35 msr CORTEX_A78_ACTLR2_EL1, x1 36 isb 371: 38 ret x17 39endfunc errata_a78_1688305_wa 40 41func check_errata_1688305 42 /* Applies to r0p0 and r1p0 */ 43 mov x1, #0x10 44 b cpu_rev_var_ls 45endfunc check_errata_1688305 46 47 /* ------------------------------------------------- 48 * The CPU Ops reset function for Cortex-A78 49 * ------------------------------------------------- 50 */ 51func cortex_a78_reset_func 52 mov x19, x30 53 bl cpu_get_rev_var 54 mov x18, x0 55 56#if ERRATA_A78_1688305 57 mov x0, x18 58 bl errata_a78_1688305_wa 59#endif 60 61#if ENABLE_AMU 62 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 63 mrs x0, actlr_el3 64 bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT 65 msr actlr_el3, x0 66 67 /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */ 68 mrs x0, actlr_el2 69 bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT 70 msr actlr_el2, x0 71 72 /* Enable group0 counters */ 73 mov x0, #CORTEX_A78_AMU_GROUP0_MASK 74 msr CPUAMCNTENSET0_EL0, x0 75 76 /* Enable group1 counters */ 77 mov x0, #CORTEX_A78_AMU_GROUP1_MASK 78 msr CPUAMCNTENSET1_EL0, x0 79#endif 80 81 isb 82 ret x19 83endfunc cortex_a78_reset_func 84 85 /* --------------------------------------------- 86 * HW will do the cache maintenance while powering down 87 * --------------------------------------------- 88 */ 89func cortex_a78_core_pwr_dwn 90 /* --------------------------------------------- 91 * Enable CPU power down bit in power control register 92 * --------------------------------------------- 93 */ 94 mrs x0, CORTEX_A78_CPUPWRCTLR_EL1 95 orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 96 msr CORTEX_A78_CPUPWRCTLR_EL1, x0 97 isb 98 ret 99endfunc cortex_a78_core_pwr_dwn 100 101 /* 102 * Errata printing function for cortex_a78. Must follow AAPCS. 103 */ 104#if REPORT_ERRATA 105func cortex_a78_errata_report 106 stp x8, x30, [sp, #-16]! 107 108 bl cpu_get_rev_var 109 mov x8, x0 110 111 /* 112 * Report all errata. The revision-variant information is passed to 113 * checking functions of each errata. 114 */ 115 report_errata ERRATA_A78_1688305, cortex_a78, 1688305 116 117 ldp x8, x30, [sp], #16 118 ret 119endfunc cortex_a78_errata_report 120#endif 121 122 /* --------------------------------------------- 123 * This function provides cortex_a78 specific 124 * register information for crash reporting. 125 * It needs to return with x6 pointing to 126 * a list of register names in ascii and 127 * x8 - x15 having values of registers to be 128 * reported. 129 * --------------------------------------------- 130 */ 131.section .rodata.cortex_a78_regs, "aS" 132cortex_a78_regs: /* The ascii list of register names to be reported */ 133 .asciz "cpuectlr_el1", "" 134 135func cortex_a78_cpu_reg_dump 136 adr x6, cortex_a78_regs 137 mrs x8, CORTEX_A78_CPUECTLR_EL1 138 ret 139endfunc cortex_a78_cpu_reg_dump 140 141declare_cpu_ops cortex_a78, CORTEX_A78_MIDR, \ 142 cortex_a78_reset_func, \ 143 cortex_a78_core_pwr_dwn 144