1/* 2 * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a77.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex-A77 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex-A77 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24 /* -------------------------------------------------- 25 * Errata Workaround for Cortex A77 Errata #1508412. 26 * This applies only to revision <= r1p0 of Cortex A77. 27 * Inputs: 28 * x0: variant[4:7] and revision[0:3] of current cpu. 29 * Shall clobber: x0-x17 30 * -------------------------------------------------- 31 */ 32func errata_a77_1508412_wa 33 /* 34 * Compare x0 against revision r1p0 35 */ 36 mov x17, x30 37 bl check_errata_1508412 38 cbz x0, 3f 39 /* 40 * Compare x0 against revision r0p0 41 */ 42 bl check_errata_1508412_0 43 cbz x0, 1f 44 ldr x0, =0x0 45 msr CORTEX_A77_CPUPSELR_EL3, x0 46 ldr x0, =0x00E8400000 47 msr CORTEX_A77_CPUPOR_EL3, x0 48 ldr x0, =0x00FFE00000 49 msr CORTEX_A77_CPUPMR_EL3, x0 50 ldr x0, =0x4004003FF 51 msr CORTEX_A77_CPUPCR_EL3, x0 52 ldr x0, =0x1 53 msr CORTEX_A77_CPUPSELR_EL3, x0 54 ldr x0, =0x00E8C00040 55 msr CORTEX_A77_CPUPOR_EL3, x0 56 ldr x0, =0x00FFE00040 57 msr CORTEX_A77_CPUPMR_EL3, x0 58 b 2f 591: 60 ldr x0, =0x0 61 msr CORTEX_A77_CPUPSELR_EL3, x0 62 ldr x0, =0x00E8400000 63 msr CORTEX_A77_CPUPOR_EL3, x0 64 ldr x0, =0x00FF600000 65 msr CORTEX_A77_CPUPMR_EL3, x0 66 ldr x0, =0x00E8E00080 67 msr CORTEX_A77_CPUPOR2_EL3, x0 68 ldr x0, =0x00FFE000C0 69 msr CORTEX_A77_CPUPMR2_EL3, x0 702: 71 ldr x0, =0x04004003FF 72 msr CORTEX_A77_CPUPCR_EL3, x0 73 isb 743: 75 ret x17 76endfunc errata_a77_1508412_wa 77 78func check_errata_1508412 79 mov x1, #0x10 80 b cpu_rev_var_ls 81endfunc check_errata_1508412 82 83func check_errata_1508412_0 84 mov x1, #0x0 85 b cpu_rev_var_ls 86endfunc check_errata_1508412_0 87 88 /* -------------------------------------------------- 89 * Errata Workaround for Cortex A77 Errata #1800714. 90 * This applies to revision <= r1p1 of Cortex A77. 91 * Inputs: 92 * x0: variant[4:7] and revision[0:3] of current cpu. 93 * Shall clobber: x0-x17 94 * -------------------------------------------------- 95 */ 96func errata_a77_1800714_wa 97 /* Compare x0 against revision <= r1p1 */ 98 mov x17, x30 99 bl check_errata_1800714 100 cbz x0, 1f 101 102 /* Disable allocation of splintered pages in the L2 TLB */ 103 mrs x1, CORTEX_A77_CPUECTLR_EL1 104 orr x1, x1, CORTEX_A77_CPUECTLR_EL1_BIT_53 105 msr CORTEX_A77_CPUECTLR_EL1, x1 106 isb 1071: 108 ret x17 109endfunc errata_a77_1800714_wa 110 111func check_errata_1800714 112 /* Applies to everything <= r1p1 */ 113 mov x1, #0x11 114 b cpu_rev_var_ls 115endfunc check_errata_1800714 116 117 /* -------------------------------------------------- 118 * Errata Workaround for Cortex A77 Errata #1925769. 119 * This applies to revision <= r1p1 of Cortex A77. 120 * Inputs: 121 * x0: variant[4:7] and revision[0:3] of current cpu. 122 * Shall clobber: x0-x17 123 * -------------------------------------------------- 124 */ 125func errata_a77_1925769_wa 126 /* Compare x0 against revision <= r1p1 */ 127 mov x17, x30 128 bl check_errata_1925769 129 cbz x0, 1f 130 131 /* Set bit 8 in ECTLR_EL1 */ 132 mrs x1, CORTEX_A77_CPUECTLR_EL1 133 orr x1, x1, #CORTEX_A77_CPUECTLR_EL1_BIT_8 134 msr CORTEX_A77_CPUECTLR_EL1, x1 135 isb 1361: 137 ret x17 138endfunc errata_a77_1925769_wa 139 140func check_errata_1925769 141 /* Applies to everything <= r1p1 */ 142 mov x1, #0x11 143 b cpu_rev_var_ls 144endfunc check_errata_1925769 145 146 /* ------------------------------------------------- 147 * The CPU Ops reset function for Cortex-A77. 148 * Shall clobber: x0-x19 149 * ------------------------------------------------- 150 */ 151func cortex_a77_reset_func 152 mov x19, x30 153 bl cpu_get_rev_var 154 mov x18, x0 155 156#if ERRATA_A77_1508412 157 mov x0, x18 158 bl errata_a77_1508412_wa 159#endif 160 161#if ERRATA_A77_1800714 162 mov x0, x18 163 bl errata_a77_1800714_wa 164#endif 165 166#if ERRATA_A77_1925769 167 mov x0, x18 168 bl errata_a77_1925769_wa 169#endif 170 171 ret x19 172endfunc cortex_a77_reset_func 173 174 /* --------------------------------------------- 175 * HW will do the cache maintenance while powering down 176 * --------------------------------------------- 177 */ 178func cortex_a77_core_pwr_dwn 179 /* --------------------------------------------- 180 * Enable CPU power down bit in power control register 181 * --------------------------------------------- 182 */ 183 mrs x0, CORTEX_A77_CPUPWRCTLR_EL1 184 orr x0, x0, #CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 185 msr CORTEX_A77_CPUPWRCTLR_EL1, x0 186 isb 187 ret 188endfunc cortex_a77_core_pwr_dwn 189 190#if REPORT_ERRATA 191/* 192 * Errata printing function for Cortex-A77. Must follow AAPCS. 193 */ 194func cortex_a77_errata_report 195 stp x8, x30, [sp, #-16]! 196 197 bl cpu_get_rev_var 198 mov x8, x0 199 200 /* 201 * Report all errata. The revision-variant information is passed to 202 * checking functions of each errata. 203 */ 204 report_errata ERRATA_A77_1508412, cortex_a77, 1508412 205 report_errata ERRATA_A77_1800714, cortex_a77, 1800714 206 report_errata ERRATA_A77_1925769, cortex_a77, 1925769 207 208 ldp x8, x30, [sp], #16 209 ret 210endfunc cortex_a77_errata_report 211#endif 212 213 214 /* --------------------------------------------- 215 * This function provides Cortex-A77 specific 216 * register information for crash reporting. 217 * It needs to return with x6 pointing to 218 * a list of register names in ascii and 219 * x8 - x15 having values of registers to be 220 * reported. 221 * --------------------------------------------- 222 */ 223.section .rodata.cortex_a77_regs, "aS" 224cortex_a77_regs: /* The ascii list of register names to be reported */ 225 .asciz "cpuectlr_el1", "" 226 227func cortex_a77_cpu_reg_dump 228 adr x6, cortex_a77_regs 229 mrs x8, CORTEX_A77_CPUECTLR_EL1 230 ret 231endfunc cortex_a77_cpu_reg_dump 232 233declare_cpu_ops cortex_a77, CORTEX_A77_MIDR, \ 234 cortex_a77_reset_func, \ 235 cortex_a77_core_pwr_dwn 236