1/* 2 * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a77.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-A77 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20cpu_reset_prologue cortex_a77 21 22/* 64-bit only core */ 23#if CTX_INCLUDE_AARCH32_REGS == 1 24#error "Cortex-A77 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 25#endif 26 27#if WORKAROUND_CVE_2022_23960 28 wa_cve_2022_23960_bhb_vector_table CORTEX_A77_BHB_LOOP_COUNT, cortex_a77 29#endif /* WORKAROUND_CVE_2022_23960 */ 30 31/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 32workaround_reset_start cortex_a77, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 33 sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, BIT(46) 34workaround_reset_end cortex_a77, CVE(2024, 5660) 35 36check_erratum_ls cortex_a77, CVE(2024, 5660), CPU_REV(1, 1) 37 38workaround_reset_start cortex_a77, ERRATUM(1508412), ERRATA_A77_1508412 39 /* move cpu revision in again and compare against r0p0 */ 40 mov x0, x7 41 cpu_rev_var_ls CPU_REV(0, 0) 42 cbz x0, 1f 43 44 ldr x0, =0x0 45 msr CORTEX_A77_CPUPSELR_EL3, x0 46 ldr x0, =0x00E8400000 47 msr CORTEX_A77_CPUPOR_EL3, x0 48 ldr x0, =0x00FFE00000 49 msr CORTEX_A77_CPUPMR_EL3, x0 50 ldr x0, =0x4004003FF 51 msr CORTEX_A77_CPUPCR_EL3, x0 52 ldr x0, =0x1 53 msr CORTEX_A77_CPUPSELR_EL3, x0 54 ldr x0, =0x00E8C00040 55 msr CORTEX_A77_CPUPOR_EL3, x0 56 ldr x0, =0x00FFE00040 57 msr CORTEX_A77_CPUPMR_EL3, x0 58 b 2f 591: 60 ldr x0, =0x0 61 msr CORTEX_A77_CPUPSELR_EL3, x0 62 ldr x0, =0x00E8400000 63 msr CORTEX_A77_CPUPOR_EL3, x0 64 ldr x0, =0x00FF600000 65 msr CORTEX_A77_CPUPMR_EL3, x0 66 ldr x0, =0x00E8E00080 67 msr CORTEX_A77_CPUPOR2_EL3, x0 68 ldr x0, =0x00FFE000C0 69 msr CORTEX_A77_CPUPMR2_EL3, x0 702: 71 ldr x0, =0x04004003FF 72 msr CORTEX_A77_CPUPCR_EL3, x0 73workaround_reset_end cortex_a77, ERRATUM(1508412) 74 75check_erratum_ls cortex_a77, ERRATUM(1508412), CPU_REV(1, 0) 76 77workaround_reset_start cortex_a77, ERRATUM(1791578), ERRATA_A77_1791578 78 sysreg_bit_set CORTEX_A77_ACTLR2_EL1, CORTEX_A77_ACTLR2_EL1_BIT_2 79workaround_reset_end cortex_a77, ERRATUM(1791578) 80 81check_erratum_ls cortex_a77, ERRATUM(1791578), CPU_REV(1, 1) 82 83workaround_reset_start cortex_a77, ERRATUM(1800714), ERRATA_A77_1800714 84 /* Disable allocation of splintered pages in the L2 TLB */ 85 sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_53 86workaround_reset_end cortex_a77, ERRATUM(1800714) 87 88check_erratum_ls cortex_a77, ERRATUM(1800714), CPU_REV(1, 1) 89 90workaround_reset_start cortex_a77, ERRATUM(1925769), ERRATA_A77_1925769 91 sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_8 92workaround_reset_end cortex_a77, ERRATUM(1925769) 93 94check_erratum_ls cortex_a77, ERRATUM(1925769), CPU_REV(1, 1) 95 96workaround_reset_start cortex_a77, ERRATUM(1946167), ERRATA_A77_1946167 97 ldr x0,=0x4 98 msr CORTEX_A77_CPUPSELR_EL3,x0 99 ldr x0,=0x10E3900002 100 msr CORTEX_A77_CPUPOR_EL3,x0 101 ldr x0,=0x10FFF00083 102 msr CORTEX_A77_CPUPMR_EL3,x0 103 ldr x0,=0x2001003FF 104 msr CORTEX_A77_CPUPCR_EL3,x0 105 106 ldr x0,=0x5 107 msr CORTEX_A77_CPUPSELR_EL3,x0 108 ldr x0,=0x10E3800082 109 msr CORTEX_A77_CPUPOR_EL3,x0 110 ldr x0,=0x10FFF00083 111 msr CORTEX_A77_CPUPMR_EL3,x0 112 ldr x0,=0x2001003FF 113 msr CORTEX_A77_CPUPCR_EL3,x0 114 115 ldr x0,=0x6 116 msr CORTEX_A77_CPUPSELR_EL3,x0 117 ldr x0,=0x10E3800200 118 msr CORTEX_A77_CPUPOR_EL3,x0 119 ldr x0,=0x10FFF003E0 120 msr CORTEX_A77_CPUPMR_EL3,x0 121 ldr x0,=0x2001003FF 122 msr CORTEX_A77_CPUPCR_EL3,x0 123workaround_reset_end cortex_a77, ERRATUM(1946167) 124 125check_erratum_ls cortex_a77, ERRATUM(1946167), CPU_REV(1, 1) 126 127workaround_reset_start cortex_a77, ERRATUM(2356587), ERRATA_A77_2356587 128 sysreg_bit_set CORTEX_A77_ACTLR2_EL1, CORTEX_A77_ACTLR2_EL1_BIT_0 129workaround_reset_end cortex_a77, ERRATUM(2356587) 130 131check_erratum_ls cortex_a77, ERRATUM(2356587), CPU_REV(1, 1) 132 133workaround_runtime_start cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100 134 /* dsb before isb of power down sequence */ 135 dsb sy 136workaround_runtime_end cortex_a77, ERRATUM(2743100), NO_ISB 137 138check_erratum_ls cortex_a77, ERRATUM(2743100), CPU_REV(1, 1) 139 140workaround_reset_start cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 141#if IMAGE_BL31 142 /* 143 * The Cortex-A77 generic vectors are overridden to apply errata 144 * mitigation on exception entry from lower ELs. 145 */ 146 adr x0, wa_cve_vbar_cortex_a77 147 msr vbar_el3, x0 148#endif /* IMAGE_BL31 */ 149workaround_reset_end cortex_a77, CVE(2022, 23960) 150 151check_erratum_chosen cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 152 153 /* ------------------------------------------------- 154 * The CPU Ops reset function for Cortex-A77. Must follow AAPCS. 155 * ------------------------------------------------- 156 */ 157cpu_reset_func_start cortex_a77 158cpu_reset_func_end cortex_a77 159 160 /* --------------------------------------------- 161 * HW will do the cache maintenance while powering down 162 * --------------------------------------------- 163 */ 164func cortex_a77_core_pwr_dwn 165 /* --------------------------------------------- 166 * Enable CPU power down bit in power control register 167 * --------------------------------------------- 168 */ 169 sysreg_bit_set CORTEX_A77_CPUPWRCTLR_EL1, \ 170 CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 171 172 apply_erratum cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100, NO_GET_CPU_REV 173 174 isb 175 ret 176endfunc cortex_a77_core_pwr_dwn 177 178 /* --------------------------------------------- 179 * This function provides Cortex-A77 specific 180 * register information for crash reporting. 181 * It needs to return with x6 pointing to 182 * a list of register names in ascii and 183 * x8 - x15 having values of registers to be 184 * reported. 185 * --------------------------------------------- 186 */ 187.section .rodata.cortex_a77_regs, "aS" 188cortex_a77_regs: /* The ascii list of register names to be reported */ 189 .asciz "cpuectlr_el1", "" 190 191func cortex_a77_cpu_reg_dump 192 adr x6, cortex_a77_regs 193 mrs x8, CORTEX_A77_CPUECTLR_EL1 194 ret 195endfunc cortex_a77_cpu_reg_dump 196 197declare_cpu_ops cortex_a77, CORTEX_A77_MIDR, \ 198 cortex_a77_reset_func, \ 199 cortex_a77_core_pwr_dwn 200