1/* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cortex_a75.h> 10#include <cpuamu.h> 11#include <cpu_macros.S> 12 13 /* -------------------------------------------------- 14 * Errata Workaround for Cortex A75 Errata #764081. 15 * This applies only to revision r0p0 of Cortex A75. 16 * Inputs: 17 * x0: variant[4:7] and revision[0:3] of current cpu. 18 * Shall clobber: x0-x17 19 * -------------------------------------------------- 20 */ 21func errata_a75_764081_wa 22 /* 23 * Compare x0 against revision r0p0 24 */ 25 mov x17, x30 26 bl check_errata_764081 27 cbz x0, 1f 28 mrs x1, sctlr_el3 29 orr x1, x1 ,#SCTLR_IESB_BIT 30 msr sctlr_el3, x1 31 isb 321: 33 ret x17 34endfunc errata_a75_764081_wa 35 36func check_errata_764081 37 mov x1, #0x00 38 b cpu_rev_var_ls 39endfunc check_errata_764081 40 41 /* -------------------------------------------------- 42 * Errata Workaround for Cortex A75 Errata #790748. 43 * This applies only to revision r0p0 of Cortex A75. 44 * Inputs: 45 * x0: variant[4:7] and revision[0:3] of current cpu. 46 * Shall clobber: x0-x17 47 * -------------------------------------------------- 48 */ 49func errata_a75_790748_wa 50 /* 51 * Compare x0 against revision r0p0 52 */ 53 mov x17, x30 54 bl check_errata_790748 55 cbz x0, 1f 56 mrs x1, CORTEX_A75_CPUACTLR_EL1 57 orr x1, x1 ,#(1 << 13) 58 msr CORTEX_A75_CPUACTLR_EL1, x1 59 isb 601: 61 ret x17 62endfunc errata_a75_790748_wa 63 64func check_errata_790748 65 mov x1, #0x00 66 b cpu_rev_var_ls 67endfunc check_errata_790748 68 69 /* ------------------------------------------------- 70 * The CPU Ops reset function for Cortex-A75. 71 * ------------------------------------------------- 72 */ 73func cortex_a75_reset_func 74 mov x19, x30 75 bl cpu_get_rev_var 76 mov x18, x0 77 78#if ERRATA_A75_764081 79 mov x0, x18 80 bl errata_a75_764081_wa 81#endif 82 83#if ERRATA_A75_790748 84 mov x0, x18 85 bl errata_a75_790748_wa 86#endif 87 88#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 89 cpu_check_csv2 x0, 1f 90 adr x0, wa_cve_2017_5715_bpiall_vbar 91 msr vbar_el3, x0 92 isb 931: 94#endif 95 96#if WORKAROUND_CVE_2018_3639 97 mrs x0, CORTEX_A75_CPUACTLR_EL1 98 orr x0, x0, #CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE 99 msr CORTEX_A75_CPUACTLR_EL1, x0 100 isb 101#endif 102 103#if ERRATA_DSU_798953 104 bl errata_dsu_798953_wa 105#endif 106 107#if ERRATA_DSU_936184 108 bl errata_dsu_936184_wa 109#endif 110 111#if ENABLE_AMU 112 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 113 mrs x0, actlr_el3 114 orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT 115 msr actlr_el3, x0 116 isb 117 118 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 119 mrs x0, actlr_el2 120 orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT 121 msr actlr_el2, x0 122 isb 123 124 /* Enable group0 counters */ 125 mov x0, #CORTEX_A75_AMU_GROUP0_MASK 126 msr CPUAMCNTENSET_EL0, x0 127 isb 128 129 /* Enable group1 counters */ 130 mov x0, #CORTEX_A75_AMU_GROUP1_MASK 131 msr CPUAMCNTENSET_EL0, x0 132 isb 133#endif 134 ret x19 135endfunc cortex_a75_reset_func 136 137func check_errata_cve_2017_5715 138 cpu_check_csv2 x0, 1f 139#if WORKAROUND_CVE_2017_5715 140 mov x0, #ERRATA_APPLIES 141#else 142 mov x0, #ERRATA_MISSING 143#endif 144 ret 1451: 146 mov x0, #ERRATA_NOT_APPLIES 147 ret 148endfunc check_errata_cve_2017_5715 149 150func check_errata_cve_2018_3639 151#if WORKAROUND_CVE_2018_3639 152 mov x0, #ERRATA_APPLIES 153#else 154 mov x0, #ERRATA_MISSING 155#endif 156 ret 157endfunc check_errata_cve_2018_3639 158 159 /* --------------------------------------------- 160 * HW will do the cache maintenance while powering down 161 * --------------------------------------------- 162 */ 163func cortex_a75_core_pwr_dwn 164 /* --------------------------------------------- 165 * Enable CPU power down bit in power control register 166 * --------------------------------------------- 167 */ 168 mrs x0, CORTEX_A75_CPUPWRCTLR_EL1 169 orr x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK 170 msr CORTEX_A75_CPUPWRCTLR_EL1, x0 171 isb 172 ret 173endfunc cortex_a75_core_pwr_dwn 174 175#if REPORT_ERRATA 176/* 177 * Errata printing function for Cortex A75. Must follow AAPCS. 178 */ 179func cortex_a75_errata_report 180 stp x8, x30, [sp, #-16]! 181 182 bl cpu_get_rev_var 183 mov x8, x0 184 185 /* 186 * Report all errata. The revision-variant information is passed to 187 * checking functions of each errata. 188 */ 189 report_errata ERRATA_A75_764081, cortex_a75, 764081 190 report_errata ERRATA_A75_790748, cortex_a75, 790748 191 report_errata WORKAROUND_CVE_2017_5715, cortex_a75, cve_2017_5715 192 report_errata WORKAROUND_CVE_2018_3639, cortex_a75, cve_2018_3639 193 report_errata ERRATA_DSU_798953, cortex_a75, dsu_798953 194 report_errata ERRATA_DSU_936184, cortex_a75, dsu_936184 195 196 ldp x8, x30, [sp], #16 197 ret 198endfunc cortex_a75_errata_report 199#endif 200 201 /* --------------------------------------------- 202 * This function provides cortex_a75 specific 203 * register information for crash reporting. 204 * It needs to return with x6 pointing to 205 * a list of register names in ascii and 206 * x8 - x15 having values of registers to be 207 * reported. 208 * --------------------------------------------- 209 */ 210.section .rodata.cortex_a75_regs, "aS" 211cortex_a75_regs: /* The ascii list of register names to be reported */ 212 .asciz "cpuectlr_el1", "" 213 214func cortex_a75_cpu_reg_dump 215 adr x6, cortex_a75_regs 216 mrs x8, CORTEX_A75_CPUECTLR_EL1 217 ret 218endfunc cortex_a75_cpu_reg_dump 219 220declare_cpu_ops_wa cortex_a75, CORTEX_A75_MIDR, \ 221 cortex_a75_reset_func, \ 222 check_errata_cve_2017_5715, \ 223 CPU_NO_EXTRA2_FUNC, \ 224 cortex_a75_core_pwr_dwn 225