1/* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cortex_a75.h> 10#include <cpuamu.h> 11#include <cpu_macros.S> 12 13func cortex_a75_reset_func 14#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 15 cpu_check_csv2 x0, 1f 16 adr x0, wa_cve_2017_5715_bpiall_vbar 17 msr vbar_el3, x0 181: 19#endif 20 21#if WORKAROUND_CVE_2018_3639 22 mrs x0, CORTEX_A75_CPUACTLR_EL1 23 orr x0, x0, #CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE 24 msr CORTEX_A75_CPUACTLR_EL1, x0 25 isb 26#endif 27 28#if ENABLE_AMU 29 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 30 mrs x0, actlr_el3 31 orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT 32 msr actlr_el3, x0 33 isb 34 35 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 36 mrs x0, actlr_el2 37 orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT 38 msr actlr_el2, x0 39 isb 40 41 /* Enable group0 counters */ 42 mov x0, #CORTEX_A75_AMU_GROUP0_MASK 43 msr CPUAMCNTENSET_EL0, x0 44 isb 45 46 /* Enable group1 counters */ 47 mov x0, #CORTEX_A75_AMU_GROUP1_MASK 48 msr CPUAMCNTENSET_EL0, x0 49 isb 50#endif 51 ret 52endfunc cortex_a75_reset_func 53 54func check_errata_cve_2017_5715 55 cpu_check_csv2 x0, 1f 56#if WORKAROUND_CVE_2017_5715 57 mov x0, #ERRATA_APPLIES 58#else 59 mov x0, #ERRATA_MISSING 60#endif 61 ret 621: 63 mov x0, #ERRATA_NOT_APPLIES 64 ret 65endfunc check_errata_cve_2017_5715 66 67func check_errata_cve_2018_3639 68#if WORKAROUND_CVE_2018_3639 69 mov x0, #ERRATA_APPLIES 70#else 71 mov x0, #ERRATA_MISSING 72#endif 73 ret 74endfunc check_errata_cve_2018_3639 75 76 /* --------------------------------------------- 77 * HW will do the cache maintenance while powering down 78 * --------------------------------------------- 79 */ 80func cortex_a75_core_pwr_dwn 81 /* --------------------------------------------- 82 * Enable CPU power down bit in power control register 83 * --------------------------------------------- 84 */ 85 mrs x0, CORTEX_A75_CPUPWRCTLR_EL1 86 orr x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK 87 msr CORTEX_A75_CPUPWRCTLR_EL1, x0 88 isb 89 ret 90endfunc cortex_a75_core_pwr_dwn 91 92#if REPORT_ERRATA 93/* 94 * Errata printing function for Cortex A75. Must follow AAPCS. 95 */ 96func cortex_a75_errata_report 97 stp x8, x30, [sp, #-16]! 98 99 bl cpu_get_rev_var 100 mov x8, x0 101 102 /* 103 * Report all errata. The revision-variant information is passed to 104 * checking functions of each errata. 105 */ 106 report_errata WORKAROUND_CVE_2017_5715, cortex_a75, cve_2017_5715 107 report_errata WORKAROUND_CVE_2018_3639, cortex_a75, cve_2018_3639 108 109 ldp x8, x30, [sp], #16 110 ret 111endfunc cortex_a75_errata_report 112#endif 113 114 /* --------------------------------------------- 115 * This function provides cortex_a75 specific 116 * register information for crash reporting. 117 * It needs to return with x6 pointing to 118 * a list of register names in ascii and 119 * x8 - x15 having values of registers to be 120 * reported. 121 * --------------------------------------------- 122 */ 123.section .rodata.cortex_a75_regs, "aS" 124cortex_a75_regs: /* The ascii list of register names to be reported */ 125 .asciz "cpuectlr_el1", "" 126 127func cortex_a75_cpu_reg_dump 128 adr x6, cortex_a75_regs 129 mrs x8, CORTEX_A75_CPUECTLR_EL1 130 ret 131endfunc cortex_a75_cpu_reg_dump 132 133declare_cpu_ops_wa cortex_a75, CORTEX_A75_MIDR, \ 134 cortex_a75_reset_func, \ 135 check_errata_cve_2017_5715, \ 136 CPU_NO_EXTRA2_FUNC, \ 137 cortex_a75_core_pwr_dwn 138