1/* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <bl_common.h> 10#include <cpu_macros.S> 11#include <plat_macros.S> 12#include <cortex_a75.h> 13 14func cortex_a75_reset_func 15#if ENABLE_AMU 16 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 17 mrs x0, actlr_el3 18 orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT 19 msr actlr_el3, x0 20 isb 21 22 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 23 mrs x0, actlr_el2 24 orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT 25 msr actlr_el2, x0 26 isb 27 28 /* Enable group0 counters */ 29 mov x0, #CORTEX_A75_AMU_GROUP0_MASK 30 msr CPUAMCNTENSET_EL0, x0 31 isb 32 33 /* Enable group1 counters */ 34 mov x0, #CORTEX_A75_AMU_GROUP1_MASK 35 msr CPUAMCNTENSET_EL0, x0 36 isb 37#endif 38 ret 39endfunc cortex_a75_reset_func 40 41 /* --------------------------------------------- 42 * HW will do the cache maintenance while powering down 43 * --------------------------------------------- 44 */ 45func cortex_a75_core_pwr_dwn 46 /* --------------------------------------------- 47 * Enable CPU power down bit in power control register 48 * --------------------------------------------- 49 */ 50 mrs x0, CORTEX_A75_CPUPWRCTLR_EL1 51 orr x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK 52 msr CORTEX_A75_CPUPWRCTLR_EL1, x0 53 isb 54 ret 55endfunc cortex_a75_core_pwr_dwn 56 57 /* --------------------------------------------- 58 * This function provides cortex_a75 specific 59 * register information for crash reporting. 60 * It needs to return with x6 pointing to 61 * a list of register names in ascii and 62 * x8 - x15 having values of registers to be 63 * reported. 64 * --------------------------------------------- 65 */ 66.section .rodata.cortex_a75_regs, "aS" 67cortex_a75_regs: /* The ascii list of register names to be reported */ 68 .asciz "cpuectlr_el1", "" 69 70func cortex_a75_cpu_reg_dump 71 adr x6, cortex_a75_regs 72 mrs x8, CORTEX_A75_CPUECTLR_EL1 73 ret 74endfunc cortex_a75_cpu_reg_dump 75 76declare_cpu_ops cortex_a75, CORTEX_A75_MIDR, \ 77 cortex_a75_reset_func, \ 78 cortex_a75_core_pwr_dwn 79