1/* 2 * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cortex_a75.h> 10#include <cpuamu.h> 11#include <cpu_macros.S> 12 13/* Hardware handled coherency */ 14#if HW_ASSISTED_COHERENCY == 0 15#error "Cortex-A75 must be compiled with HW_ASSISTED_COHERENCY enabled" 16#endif 17 18workaround_reset_start cortex_a75, ERRATUM(764081), ERRATA_A75_764081 19 mrs x1, sctlr_el3 20 orr x1, x1 ,#SCTLR_IESB_BIT 21 msr sctlr_el3, x1 22workaround_reset_end cortex_a75, ERRATUM(764081) 23 24check_erratum_ls cortex_a75, ERRATUM(764081), CPU_REV(0, 0) 25 26workaround_reset_start cortex_a75, ERRATUM(790748), ERRATA_A75_790748 27 mrs x1, CORTEX_A75_CPUACTLR_EL1 28 orr x1, x1 ,#(1 << 13) 29 msr CORTEX_A75_CPUACTLR_EL1, x1 30workaround_reset_end cortex_a75, ERRATUM(790748) 31 32check_erratum_ls cortex_a75, ERRATUM(790748), CPU_REV(0, 0) 33 34/* ERRATA_DSU_798953 : 35 * The errata is defined in dsu_helpers.S but applies to cortex_a75 36 * as well. Henceforth creating symbolic names to the already existing errata 37 * workaround functions to get them registered under the Errata Framework. 38 */ 39.equ check_erratum_cortex_a75_798953, check_errata_dsu_798953 40.equ erratum_cortex_a75_798953_wa, errata_dsu_798953_wa 41add_erratum_entry cortex_a75, ERRATUM(798953), ERRATA_DSU_798953, APPLY_AT_RESET 42 43/* ERRATA_DSU_936184 : 44 * The errata is defined in dsu_helpers.S but applies to cortex_a75 45 * as well. Henceforth creating symbolic names to the already existing errata 46 * workaround functions to get them registered under the Errata Framework. 47 */ 48.equ check_erratum_cortex_a75_936184, check_errata_dsu_936184 49.equ erratum_cortex_a75_936184_wa, errata_dsu_936184_wa 50add_erratum_entry cortex_a75, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET 51 52workaround_reset_start cortex_a75, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 53#if IMAGE_BL31 54 adr x0, wa_cve_2017_5715_bpiall_vbar 55 msr vbar_el3, x0 56#endif /* IMAGE_BL31 */ 57workaround_reset_end cortex_a75, CVE(2017, 5715) 58 59check_erratum_custom_start cortex_a75, CVE(2017, 5715) 60 cpu_check_csv2 x0, 1f 61#if WORKAROUND_CVE_2017_5715 62 mov x0, #ERRATA_APPLIES 63#else 64 mov x0, #ERRATA_MISSING 65#endif 66 ret 671: 68 mov x0, #ERRATA_NOT_APPLIES 69 ret 70check_erratum_custom_end cortex_a75, CVE(2017, 5715) 71 72workaround_reset_start cortex_a75, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 73 mrs x0, CORTEX_A75_CPUACTLR_EL1 74 orr x0, x0, #CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE 75 msr CORTEX_A75_CPUACTLR_EL1, x0 76workaround_reset_end cortex_a75, CVE(2018, 3639) 77 78check_erratum_chosen cortex_a75, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 79 80workaround_reset_start cortex_a75, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 81#if IMAGE_BL31 82 /* Skip installing vector table again if already done for CVE(2017, 5715) */ 83 adr x0, wa_cve_2017_5715_bpiall_vbar 84 mrs x1, vbar_el3 85 cmp x0, x1 86 b.eq 1f 87 msr vbar_el3, x0 881: 89#endif /* IMAGE_BL31 */ 90workaround_reset_end cortex_a75, CVE(2022, 23960) 91 92check_erratum_custom_start cortex_a75, CVE(2022, 23960) 93#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 94 cpu_check_csv2 x0, 1f 95 mov x0, #ERRATA_APPLIES 96 ret 971: 98# if WORKAROUND_CVE_2022_23960 99 mov x0, #ERRATA_APPLIES 100# else 101 mov x0, #ERRATA_MISSING 102# endif /* WORKAROUND_CVE_2022_23960 */ 103 ret 104#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */ 105 mov x0, #ERRATA_MISSING 106 ret 107check_erratum_custom_end cortex_a75, CVE(2022, 23960) 108 109 /* ------------------------------------------------- 110 * The CPU Ops reset function for Cortex-A75. 111 * ------------------------------------------------- 112 */ 113 114cpu_reset_func_start cortex_a75 115#if ENABLE_FEAT_AMU 116 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 117 mrs x0, actlr_el3 118 orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT 119 msr actlr_el3, x0 120 isb 121 122 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 123 mrs x0, actlr_el2 124 orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT 125 msr actlr_el2, x0 126 isb 127 128 /* Enable group0 counters */ 129 mov x0, #CORTEX_A75_AMU_GROUP0_MASK 130 msr CPUAMCNTENSET_EL0, x0 131 isb 132 133 /* Enable group1 counters */ 134 mov x0, #CORTEX_A75_AMU_GROUP1_MASK 135 msr CPUAMCNTENSET_EL0, x0 136 /* isb included in cpu_reset_func_end macro */ 137#endif 138cpu_reset_func_end cortex_a75 139 140func check_smccc_arch_workaround_3 141 mov x0, #ERRATA_APPLIES 142 ret 143endfunc check_smccc_arch_workaround_3 144 145 /* --------------------------------------------- 146 * HW will do the cache maintenance while powering down 147 * --------------------------------------------- 148 */ 149func cortex_a75_core_pwr_dwn 150 /* --------------------------------------------- 151 * Enable CPU power down bit in power control register 152 * --------------------------------------------- 153 */ 154 mrs x0, CORTEX_A75_CPUPWRCTLR_EL1 155 orr x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK 156 msr CORTEX_A75_CPUPWRCTLR_EL1, x0 157 isb 158 ret 159endfunc cortex_a75_core_pwr_dwn 160 161errata_report_shim cortex_a75 162 163 /* --------------------------------------------- 164 * This function provides cortex_a75 specific 165 * register information for crash reporting. 166 * It needs to return with x6 pointing to 167 * a list of register names in ascii and 168 * x8 - x15 having values of registers to be 169 * reported. 170 * --------------------------------------------- 171 */ 172.section .rodata.cortex_a75_regs, "aS" 173cortex_a75_regs: /* The ascii list of register names to be reported */ 174 .asciz "cpuectlr_el1", "" 175 176func cortex_a75_cpu_reg_dump 177 adr x6, cortex_a75_regs 178 mrs x8, CORTEX_A75_CPUECTLR_EL1 179 ret 180endfunc cortex_a75_cpu_reg_dump 181 182declare_cpu_ops_wa cortex_a75, CORTEX_A75_MIDR, \ 183 cortex_a75_reset_func, \ 184 check_erratum_cortex_a75_5715, \ 185 CPU_NO_EXTRA2_FUNC, \ 186 check_smccc_arch_workaround_3, \ 187 cortex_a75_core_pwr_dwn 188