1/* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cortex_a75.h> 10#include <cpuamu.h> 11#include <cpu_macros.S> 12 13func cortex_a75_reset_func 14#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 15 mrs x0, id_aa64pfr0_el1 16 ubfx x0, x0, #ID_AA64PFR0_CSV2_SHIFT, #ID_AA64PFR0_CSV2_LENGTH 17 /* 18 * If the field equals to 1 then branch targets trained in one 19 * context cannot affect speculative execution in a different context. 20 */ 21 cmp x0, #1 22 beq 1f 23 24 adr x0, workaround_bpiall_vbar0_runtime_exceptions 25 msr vbar_el3, x0 261: 27#endif 28 29#if ENABLE_AMU 30 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 31 mrs x0, actlr_el3 32 orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT 33 msr actlr_el3, x0 34 isb 35 36 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 37 mrs x0, actlr_el2 38 orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT 39 msr actlr_el2, x0 40 isb 41 42 /* Enable group0 counters */ 43 mov x0, #CORTEX_A75_AMU_GROUP0_MASK 44 msr CPUAMCNTENSET_EL0, x0 45 isb 46 47 /* Enable group1 counters */ 48 mov x0, #CORTEX_A75_AMU_GROUP1_MASK 49 msr CPUAMCNTENSET_EL0, x0 50 isb 51#endif 52 ret 53endfunc cortex_a75_reset_func 54 55func check_errata_cve_2017_5715 56 mrs x0, id_aa64pfr0_el1 57 ubfx x0, x0, #ID_AA64PFR0_CSV2_SHIFT, #ID_AA64PFR0_CSV2_LENGTH 58 /* 59 * If the field equals to 1 then branch targets trained in one 60 * context cannot affect speculative execution in a different context. 61 */ 62 cmp x0, #1 63 beq 1f 64 65#if WORKAROUND_CVE_2017_5715 66 mov x0, #ERRATA_APPLIES 67#else 68 mov x0, #ERRATA_MISSING 69#endif 70 ret 711: 72 mov x0, #ERRATA_NOT_APPLIES 73 ret 74endfunc check_errata_cve_2017_5715 75 76 /* --------------------------------------------- 77 * HW will do the cache maintenance while powering down 78 * --------------------------------------------- 79 */ 80func cortex_a75_core_pwr_dwn 81 /* --------------------------------------------- 82 * Enable CPU power down bit in power control register 83 * --------------------------------------------- 84 */ 85 mrs x0, CORTEX_A75_CPUPWRCTLR_EL1 86 orr x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK 87 msr CORTEX_A75_CPUPWRCTLR_EL1, x0 88 isb 89 ret 90endfunc cortex_a75_core_pwr_dwn 91 92#if REPORT_ERRATA 93/* 94 * Errata printing function for Cortex A75. Must follow AAPCS. 95 */ 96func cortex_a75_errata_report 97 stp x8, x30, [sp, #-16]! 98 99 bl cpu_get_rev_var 100 mov x8, x0 101 102 /* 103 * Report all errata. The revision-variant information is passed to 104 * checking functions of each errata. 105 */ 106 report_errata WORKAROUND_CVE_2017_5715, cortex_a75, cve_2017_5715 107 108 ldp x8, x30, [sp], #16 109 ret 110endfunc cortex_a75_errata_report 111#endif 112 113 /* --------------------------------------------- 114 * This function provides cortex_a75 specific 115 * register information for crash reporting. 116 * It needs to return with x6 pointing to 117 * a list of register names in ascii and 118 * x8 - x15 having values of registers to be 119 * reported. 120 * --------------------------------------------- 121 */ 122.section .rodata.cortex_a75_regs, "aS" 123cortex_a75_regs: /* The ascii list of register names to be reported */ 124 .asciz "cpuectlr_el1", "" 125 126func cortex_a75_cpu_reg_dump 127 adr x6, cortex_a75_regs 128 mrs x8, CORTEX_A75_CPUECTLR_EL1 129 ret 130endfunc cortex_a75_cpu_reg_dump 131 132declare_cpu_ops cortex_a75, CORTEX_A75_MIDR, \ 133 cortex_a75_reset_func, \ 134 cortex_a75_core_pwr_dwn 135