1/* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cortex_a75.h> 10#include <cpuamu.h> 11#include <cpu_macros.S> 12 13func cortex_a75_reset_func 14#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 15 cpu_check_csv2 x0, 1f 16 adr x0, wa_cve_2017_5715_bpiall_vbar 17 msr vbar_el3, x0 18 isb 191: 20#endif 21 22#if WORKAROUND_CVE_2018_3639 23 mrs x0, CORTEX_A75_CPUACTLR_EL1 24 orr x0, x0, #CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE 25 msr CORTEX_A75_CPUACTLR_EL1, x0 26 isb 27#endif 28 29#if ENABLE_AMU 30 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 31 mrs x0, actlr_el3 32 orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT 33 msr actlr_el3, x0 34 isb 35 36 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 37 mrs x0, actlr_el2 38 orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT 39 msr actlr_el2, x0 40 isb 41 42 /* Enable group0 counters */ 43 mov x0, #CORTEX_A75_AMU_GROUP0_MASK 44 msr CPUAMCNTENSET_EL0, x0 45 isb 46 47 /* Enable group1 counters */ 48 mov x0, #CORTEX_A75_AMU_GROUP1_MASK 49 msr CPUAMCNTENSET_EL0, x0 50 isb 51#endif 52 ret 53endfunc cortex_a75_reset_func 54 55func check_errata_cve_2017_5715 56 cpu_check_csv2 x0, 1f 57#if WORKAROUND_CVE_2017_5715 58 mov x0, #ERRATA_APPLIES 59#else 60 mov x0, #ERRATA_MISSING 61#endif 62 ret 631: 64 mov x0, #ERRATA_NOT_APPLIES 65 ret 66endfunc check_errata_cve_2017_5715 67 68func check_errata_cve_2018_3639 69#if WORKAROUND_CVE_2018_3639 70 mov x0, #ERRATA_APPLIES 71#else 72 mov x0, #ERRATA_MISSING 73#endif 74 ret 75endfunc check_errata_cve_2018_3639 76 77 /* --------------------------------------------- 78 * HW will do the cache maintenance while powering down 79 * --------------------------------------------- 80 */ 81func cortex_a75_core_pwr_dwn 82 /* --------------------------------------------- 83 * Enable CPU power down bit in power control register 84 * --------------------------------------------- 85 */ 86 mrs x0, CORTEX_A75_CPUPWRCTLR_EL1 87 orr x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK 88 msr CORTEX_A75_CPUPWRCTLR_EL1, x0 89 isb 90 ret 91endfunc cortex_a75_core_pwr_dwn 92 93#if REPORT_ERRATA 94/* 95 * Errata printing function for Cortex A75. Must follow AAPCS. 96 */ 97func cortex_a75_errata_report 98 stp x8, x30, [sp, #-16]! 99 100 bl cpu_get_rev_var 101 mov x8, x0 102 103 /* 104 * Report all errata. The revision-variant information is passed to 105 * checking functions of each errata. 106 */ 107 report_errata WORKAROUND_CVE_2017_5715, cortex_a75, cve_2017_5715 108 report_errata WORKAROUND_CVE_2018_3639, cortex_a75, cve_2018_3639 109 110 ldp x8, x30, [sp], #16 111 ret 112endfunc cortex_a75_errata_report 113#endif 114 115 /* --------------------------------------------- 116 * This function provides cortex_a75 specific 117 * register information for crash reporting. 118 * It needs to return with x6 pointing to 119 * a list of register names in ascii and 120 * x8 - x15 having values of registers to be 121 * reported. 122 * --------------------------------------------- 123 */ 124.section .rodata.cortex_a75_regs, "aS" 125cortex_a75_regs: /* The ascii list of register names to be reported */ 126 .asciz "cpuectlr_el1", "" 127 128func cortex_a75_cpu_reg_dump 129 adr x6, cortex_a75_regs 130 mrs x8, CORTEX_A75_CPUECTLR_EL1 131 ret 132endfunc cortex_a75_cpu_reg_dump 133 134declare_cpu_ops_wa cortex_a75, CORTEX_A75_MIDR, \ 135 cortex_a75_reset_func, \ 136 check_errata_cve_2017_5715, \ 137 CPU_NO_EXTRA2_FUNC, \ 138 cortex_a75_core_pwr_dwn 139