1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a725.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-A725 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-A725 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25cpu_reset_prologue cortex_a725 26 27.global check_erratum_cortex_a725_3699564 28 29workaround_reset_start cortex_a725, ERRATUM(2900952), ERRATA_DSU_2900952 30 errata_dsu_2900952_wa_apply 31workaround_reset_end cortex_a725, ERRATUM(2900952) 32 33check_erratum_custom_start cortex_a725, ERRATUM(2900952) 34 check_errata_dsu_2900952_applies 35 ret 36check_erratum_custom_end cortex_a725, ERRATUM(2900952) 37 38add_erratum_entry cortex_a725, ERRATUM(3699564), ERRATA_A725_3699564 39 40check_erratum_ls cortex_a725, ERRATUM(3699564), CPU_REV(0, 1) 41 42cpu_reset_func_start cortex_a725 43 /* Disable speculative loads */ 44 msr SSBS, xzr 45 enable_mpmm 46cpu_reset_func_end cortex_a725 47 48 /* ---------------------------------------------------- 49 * HW will do the cache maintenance while powering down 50 * ---------------------------------------------------- 51 */ 52func cortex_a725_core_pwr_dwn 53 /* --------------------------------------------------- 54 * Enable CPU power down bit in power control register 55 * --------------------------------------------------- 56 */ 57 sysreg_bit_set CORTEX_A725_CPUPWRCTLR_EL1, CORTEX_A725_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 58 isb 59 ret 60endfunc cortex_a725_core_pwr_dwn 61 62 /* --------------------------------------------- 63 * This function provides Cortex-A725 specific 64 * register information for crash reporting. 65 * It needs to return with x6 pointing to 66 * a list of register names in ascii and 67 * x8 - x15 having values of registers to be 68 * reported. 69 * --------------------------------------------- 70 */ 71.section .rodata.cortex_a725_regs, "aS" 72cortex_a725_regs: /* The ascii list of register names to be reported */ 73 .asciz "cpuectlr_el1", "" 74 75func cortex_a725_cpu_reg_dump 76 adr x6, cortex_a725_regs 77 mrs x8, CORTEX_A725_CPUECTLR_EL1 78 ret 79endfunc cortex_a725_cpu_reg_dump 80 81declare_cpu_ops cortex_a725, CORTEX_A725_MIDR, \ 82 cortex_a725_reset_func, \ 83 cortex_a725_core_pwr_dwn 84