1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a720.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14#include "wa_cve_2022_23960_bhb_vector.S" 15 16/* Hardware handled coherency */ 17#if HW_ASSISTED_COHERENCY == 0 18#error "Cortex A720 must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21/* 64-bit only core */ 22#if CTX_INCLUDE_AARCH32_REGS == 1 23#error "Cortex A720 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 24#endif 25 26cpu_reset_prologue cortex_a720 27 28.global check_erratum_cortex_a720_3699561 29 30#if WORKAROUND_CVE_2022_23960 31 wa_cve_2022_23960_bhb_vector_table CORTEX_A720_BHB_LOOP_COUNT, cortex_a720 32#endif /* WORKAROUND_CVE_2022_23960 */ 33 34workaround_reset_start cortex_a720, ERRATUM(2729604), ERRATA_A720_2729604 35 sysreg_bit_set CORTEX_A720_CPUACTLR_EL1, (BIT(60) | BIT(61)) 36workaround_reset_end cortex_a720, ERRATUM(2729604) 37 38check_erratum_ls cortex_a720, ERRATUM(2729604), CPU_REV(0, 1) 39 40workaround_reset_start cortex_a720, ERRATUM(2792132), ERRATA_A720_2792132 41 sysreg_bit_set CORTEX_A720_CPUACTLR2_EL1, BIT(26) 42workaround_reset_end cortex_a720, ERRATUM(2792132) 43 44check_erratum_ls cortex_a720, ERRATUM(2792132), CPU_REV(0, 1) 45 46workaround_reset_start cortex_a720, ERRATUM(2844092), ERRATA_A720_2844092 47 sysreg_bit_set CORTEX_A720_CPUACTLR4_EL1, BIT(11) 48workaround_reset_end cortex_a720, ERRATUM(2844092) 49 50check_erratum_ls cortex_a720, ERRATUM(2844092), CPU_REV(0, 1) 51 52workaround_reset_start cortex_a720, ERRATUM(2900952), ERRATA_DSU_2900952 53 errata_dsu_2900952_wa_apply 54workaround_reset_end cortex_a720, ERRATUM(2900952) 55 56check_erratum_custom_start cortex_a720, ERRATUM(2900952) 57 check_errata_dsu_2900952_applies 58 ret 59check_erratum_custom_end cortex_a720, ERRATUM(2900952) 60 61workaround_reset_start cortex_a720, ERRATUM(2926083), ERRATA_A720_2926083 62/* Erratum 2926083 workaround is required only if SPE is enabled */ 63#if ENABLE_SPE_FOR_NS != 0 64 /* Check if Static profiling extension is implemented or present. */ 65 mrs x1, id_aa64dfr0_el1 66 ubfx x0, x1, ID_AA64DFR0_PMS_SHIFT, #4 67 cbz x0, 1f 68 /* Apply the workaround by setting CPUACTLR_EL1[58:57] = 0b11. */ 69 sysreg_bit_set CORTEX_A720_CPUACTLR_EL1, BIT(57) 70 sysreg_bit_set CORTEX_A720_CPUACTLR_EL1, BIT(58) 711: 72#endif 73workaround_reset_end cortex_a720, ERRATUM(2926083) 74 75check_erratum_ls cortex_a720, ERRATUM(2926083), CPU_REV(0, 1) 76 77workaround_reset_start cortex_a720, ERRATUM(2940794), ERRATA_A720_2940794 78 sysreg_bit_set CORTEX_A720_CPUACTLR2_EL1, BIT(37) 79workaround_reset_end cortex_a720, ERRATUM(2940794) 80 81check_erratum_ls cortex_a720, ERRATUM(2940794), CPU_REV(0, 1) 82 83add_erratum_entry cortex_a720, ERRATUM(3699561), ERRATA_A720_3699561 84 85check_erratum_ls cortex_a720, ERRATUM(3699561), CPU_REV(0, 2) 86 87workaround_reset_start cortex_a720, ERRATUM(3711910), ERRATA_A720_3711910 88 mov x0, #5 89 msr CORTEX_A720_CPUPSELR_EL3, x0 90 ldr x0, =0xD503329F 91 msr CORTEX_A720_CPUPOR_EL3, x0 92 ldr x0, =0xFFFFF3FF 93 msr CORTEX_A720_CPUPMR_EL3, x0 94 ldr x0, =0x1004003F1 95 msr CORTEX_A720_CPUPCR_EL3, x0 96workaround_reset_end cortex_a720, ERRATUM(3711910) 97 98check_erratum_ls cortex_a720, ERRATUM(3711910), CPU_REV(0, 2) 99 100workaround_reset_start cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 101#if IMAGE_BL31 102 /* 103 * The Cortex A720 generic vectors are overridden to apply errata 104 * mitigation on exception entry from lower ELs. 105 */ 106 override_vector_table wa_cve_vbar_cortex_a720 107#endif /* IMAGE_BL31 */ 108workaround_reset_end cortex_a720, CVE(2022, 23960) 109 110check_erratum_chosen cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 111 112cpu_reset_func_start cortex_a720 113 /* Disable speculative loads */ 114 msr SSBS, xzr 115 enable_mpmm 116cpu_reset_func_end cortex_a720 117 118 /* ---------------------------------------------------- 119 * HW will do the cache maintenance while powering down 120 * ---------------------------------------------------- 121 */ 122func cortex_a720_core_pwr_dwn 123 /* --------------------------------------------------- 124 * Enable CPU power down bit in power control register 125 * --------------------------------------------------- 126 */ 127 sysreg_bit_set CORTEX_A720_CPUPWRCTLR_EL1, CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 128 129 isb 130 ret 131endfunc cortex_a720_core_pwr_dwn 132 133 /* --------------------------------------------- 134 * This function provides Cortex A720-specific 135 * register information for crash reporting. 136 * It needs to return with x6 pointing to 137 * a list of register names in ascii and 138 * x8 - x15 having values of registers to be 139 * reported. 140 * --------------------------------------------- 141 */ 142.section .rodata.cortex_a720_regs, "aS" 143cortex_a720_regs: /* The ascii list of register names to be reported */ 144 .asciz "cpuectlr_el1", "" 145 146func cortex_a720_cpu_reg_dump 147 adr x6, cortex_a720_regs 148 mrs x8, CORTEX_A720_CPUECTLR_EL1 149 ret 150endfunc cortex_a720_cpu_reg_dump 151 152declare_cpu_ops cortex_a720, CORTEX_A720_MIDR, \ 153 cortex_a720_reset_func, \ 154 cortex_a720_core_pwr_dwn 155