1/* 2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a720.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex A720 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex A720 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_A720_BHB_LOOP_COUNT, cortex_a720 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29workaround_reset_start cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 30#if IMAGE_BL31 31 /* 32 * The Cortex A720 generic vectors are overridden to apply errata 33 * mitigation on exception entry from lower ELs. 34 */ 35 override_vector_table wa_cve_vbar_cortex_a720 36#endif /* IMAGE_BL31 */ 37workaround_reset_end cortex_a720, CVE(2022, 23960) 38 39check_erratum_chosen cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 40 41cpu_reset_func_start cortex_a720 42 /* Disable speculative loads */ 43 msr SSBS, xzr 44cpu_reset_func_end cortex_a720 45 46 /* ---------------------------------------------------- 47 * HW will do the cache maintenance while powering down 48 * ---------------------------------------------------- 49 */ 50func cortex_a720_core_pwr_dwn 51 /* --------------------------------------------------- 52 * Enable CPU power down bit in power control register 53 * --------------------------------------------------- 54 */ 55 sysreg_bit_set CORTEX_A720_CPUPWRCTLR_EL1, CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 56 57 isb 58 ret 59endfunc cortex_a720_core_pwr_dwn 60 61errata_report_shim cortex_a720 62 63 /* --------------------------------------------- 64 * This function provides Cortex A720-specific 65 * register information for crash reporting. 66 * It needs to return with x6 pointing to 67 * a list of register names in ascii and 68 * x8 - x15 having values of registers to be 69 * reported. 70 * --------------------------------------------- 71 */ 72.section .rodata.cortex_a720_regs, "aS" 73cortex_a720_regs: /* The ascii list of register names to be reported */ 74 .asciz "cpuectlr_el1", "" 75 76func cortex_a720_cpu_reg_dump 77 adr x6, cortex_a720_regs 78 mrs x8, CORTEX_A720_CPUECTLR_EL1 79 ret 80endfunc cortex_a720_cpu_reg_dump 81 82declare_cpu_ops cortex_a720, CORTEX_A720_MIDR, \ 83 cortex_a720_reset_func, \ 84 cortex_a720_core_pwr_dwn 85