1/* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <assert_macros.S> 9#include <cortex_a72.h> 10#include <cpu_macros.S> 11#include <plat_macros.S> 12 13 /* --------------------------------------------- 14 * Disable L1 data cache and unified L2 cache 15 * --------------------------------------------- 16 */ 17func cortex_a72_disable_dcache 18 mrs x1, sctlr_el3 19 bic x1, x1, #SCTLR_C_BIT 20 msr sctlr_el3, x1 21 isb 22 ret 23endfunc cortex_a72_disable_dcache 24 25 /* --------------------------------------------- 26 * Disable all types of L2 prefetches. 27 * --------------------------------------------- 28 */ 29func cortex_a72_disable_l2_prefetch 30 mrs x0, CORTEX_A72_ECTLR_EL1 31 orr x0, x0, #CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT 32 mov x1, #CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK 33 orr x1, x1, #CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK 34 bic x0, x0, x1 35 msr CORTEX_A72_ECTLR_EL1, x0 36 isb 37 ret 38endfunc cortex_a72_disable_l2_prefetch 39 40 /* --------------------------------------------- 41 * Disable the load-store hardware prefetcher. 42 * --------------------------------------------- 43 */ 44func cortex_a72_disable_hw_prefetcher 45 mrs x0, CORTEX_A72_CPUACTLR_EL1 46 orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH 47 msr CORTEX_A72_CPUACTLR_EL1, x0 48 isb 49 dsb ish 50 ret 51endfunc cortex_a72_disable_hw_prefetcher 52 53 /* --------------------------------------------- 54 * Disable intra-cluster coherency 55 * --------------------------------------------- 56 */ 57func cortex_a72_disable_smp 58 mrs x0, CORTEX_A72_ECTLR_EL1 59 bic x0, x0, #CORTEX_A72_ECTLR_SMP_BIT 60 msr CORTEX_A72_ECTLR_EL1, x0 61 ret 62endfunc cortex_a72_disable_smp 63 64 /* --------------------------------------------- 65 * Disable debug interfaces 66 * --------------------------------------------- 67 */ 68func cortex_a72_disable_ext_debug 69 mov x0, #1 70 msr osdlr_el1, x0 71 isb 72 dsb sy 73 ret 74endfunc cortex_a72_disable_ext_debug 75 76 /* -------------------------------------------------- 77 * Errata Workaround for Cortex A72 Errata #859971. 78 * This applies only to revision <= r0p3 of Cortex A72. 79 * Inputs: 80 * x0: variant[4:7] and revision[0:3] of current cpu. 81 * Shall clobber: 82 * -------------------------------------------------- 83 */ 84func errata_a72_859971_wa 85 mov x17,x30 86 bl check_errata_859971 87 cbz x0, 1f 88 mrs x1, CORTEX_A72_CPUACTLR_EL1 89 orr x1, x1, #CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH 90 msr CORTEX_A72_CPUACTLR_EL1, x1 911: 92 ret x17 93endfunc errata_a72_859971_wa 94 95func check_errata_859971 96 mov x1, #0x03 97 b cpu_rev_var_ls 98endfunc check_errata_859971 99 100 /* ------------------------------------------------- 101 * The CPU Ops reset function for Cortex-A72. 102 * ------------------------------------------------- 103 */ 104func cortex_a72_reset_func 105 mov x19, x30 106 bl cpu_get_rev_var 107 mov x18, x0 108 109#if ERRATA_A72_859971 110 mov x0, x18 111 bl errata_a72_859971_wa 112#endif 113 114#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 115 adr x0, workaround_mmu_runtime_exceptions 116 msr vbar_el3, x0 117#endif 118 119 /* --------------------------------------------- 120 * Enable the SMP bit. 121 * --------------------------------------------- 122 */ 123 mrs x0, CORTEX_A72_ECTLR_EL1 124 orr x0, x0, #CORTEX_A72_ECTLR_SMP_BIT 125 msr CORTEX_A72_ECTLR_EL1, x0 126 isb 127 ret x19 128endfunc cortex_a72_reset_func 129 130 /* ---------------------------------------------------- 131 * The CPU Ops core power down function for Cortex-A72. 132 * ---------------------------------------------------- 133 */ 134func cortex_a72_core_pwr_dwn 135 mov x18, x30 136 137 /* --------------------------------------------- 138 * Turn off caches. 139 * --------------------------------------------- 140 */ 141 bl cortex_a72_disable_dcache 142 143 /* --------------------------------------------- 144 * Disable the L2 prefetches. 145 * --------------------------------------------- 146 */ 147 bl cortex_a72_disable_l2_prefetch 148 149 /* --------------------------------------------- 150 * Disable the load-store hardware prefetcher. 151 * --------------------------------------------- 152 */ 153 bl cortex_a72_disable_hw_prefetcher 154 155 /* --------------------------------------------- 156 * Flush L1 caches. 157 * --------------------------------------------- 158 */ 159 mov x0, #DCCISW 160 bl dcsw_op_level1 161 162 /* --------------------------------------------- 163 * Come out of intra cluster coherency 164 * --------------------------------------------- 165 */ 166 bl cortex_a72_disable_smp 167 168 /* --------------------------------------------- 169 * Force the debug interfaces to be quiescent 170 * --------------------------------------------- 171 */ 172 mov x30, x18 173 b cortex_a72_disable_ext_debug 174endfunc cortex_a72_core_pwr_dwn 175 176 /* ------------------------------------------------------- 177 * The CPU Ops cluster power down function for Cortex-A72. 178 * ------------------------------------------------------- 179 */ 180func cortex_a72_cluster_pwr_dwn 181 mov x18, x30 182 183 /* --------------------------------------------- 184 * Turn off caches. 185 * --------------------------------------------- 186 */ 187 bl cortex_a72_disable_dcache 188 189 /* --------------------------------------------- 190 * Disable the L2 prefetches. 191 * --------------------------------------------- 192 */ 193 bl cortex_a72_disable_l2_prefetch 194 195 /* --------------------------------------------- 196 * Disable the load-store hardware prefetcher. 197 * --------------------------------------------- 198 */ 199 bl cortex_a72_disable_hw_prefetcher 200 201#if !SKIP_A72_L1_FLUSH_PWR_DWN 202 /* --------------------------------------------- 203 * Flush L1 caches. 204 * --------------------------------------------- 205 */ 206 mov x0, #DCCISW 207 bl dcsw_op_level1 208#endif 209 210 /* --------------------------------------------- 211 * Disable the optional ACP. 212 * --------------------------------------------- 213 */ 214 bl plat_disable_acp 215 216 /* ------------------------------------------------- 217 * Flush the L2 caches. 218 * ------------------------------------------------- 219 */ 220 mov x0, #DCCISW 221 bl dcsw_op_level2 222 223 /* --------------------------------------------- 224 * Come out of intra cluster coherency 225 * --------------------------------------------- 226 */ 227 bl cortex_a72_disable_smp 228 229 /* --------------------------------------------- 230 * Force the debug interfaces to be quiescent 231 * --------------------------------------------- 232 */ 233 mov x30, x18 234 b cortex_a72_disable_ext_debug 235endfunc cortex_a72_cluster_pwr_dwn 236 237#if REPORT_ERRATA 238/* 239 * Errata printing function for Cortex A72. Must follow AAPCS. 240 */ 241func cortex_a72_errata_report 242 stp x8, x30, [sp, #-16]! 243 244 bl cpu_get_rev_var 245 mov x8, x0 246 247 /* 248 * Report all errata. The revision-variant information is passed to 249 * checking functions of each errata. 250 */ 251 report_errata ERRATA_A72_859971, cortex_a72, 859971 252 253 ldp x8, x30, [sp], #16 254 ret 255endfunc cortex_a72_errata_report 256#endif 257 258 /* --------------------------------------------- 259 * This function provides cortex_a72 specific 260 * register information for crash reporting. 261 * It needs to return with x6 pointing to 262 * a list of register names in ascii and 263 * x8 - x15 having values of registers to be 264 * reported. 265 * --------------------------------------------- 266 */ 267.section .rodata.cortex_a72_regs, "aS" 268cortex_a72_regs: /* The ascii list of register names to be reported */ 269 .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" 270 271func cortex_a72_cpu_reg_dump 272 adr x6, cortex_a72_regs 273 mrs x8, CORTEX_A72_ECTLR_EL1 274 mrs x9, CORTEX_A72_MERRSR_EL1 275 mrs x10, CORTEX_A72_L2MERRSR_EL1 276 ret 277endfunc cortex_a72_cpu_reg_dump 278 279 280declare_cpu_ops cortex_a72, CORTEX_A72_MIDR, \ 281 cortex_a72_reset_func, \ 282 cortex_a72_core_pwr_dwn, \ 283 cortex_a72_cluster_pwr_dwn 284