1/* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <assert_macros.S> 9#include <cortex_a72.h> 10#include <cpu_macros.S> 11#include <plat_macros.S> 12 13 /* --------------------------------------------- 14 * Disable L1 data cache and unified L2 cache 15 * --------------------------------------------- 16 */ 17func cortex_a72_disable_dcache 18 mrs x1, sctlr_el3 19 bic x1, x1, #SCTLR_C_BIT 20 msr sctlr_el3, x1 21 isb 22 ret 23endfunc cortex_a72_disable_dcache 24 25 /* --------------------------------------------- 26 * Disable all types of L2 prefetches. 27 * --------------------------------------------- 28 */ 29func cortex_a72_disable_l2_prefetch 30 mrs x0, CORTEX_A72_ECTLR_EL1 31 orr x0, x0, #CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT 32 mov x1, #CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK 33 orr x1, x1, #CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK 34 bic x0, x0, x1 35 msr CORTEX_A72_ECTLR_EL1, x0 36 isb 37 ret 38endfunc cortex_a72_disable_l2_prefetch 39 40 /* --------------------------------------------- 41 * Disable the load-store hardware prefetcher. 42 * --------------------------------------------- 43 */ 44func cortex_a72_disable_hw_prefetcher 45 mrs x0, CORTEX_A72_CPUACTLR_EL1 46 orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH 47 msr CORTEX_A72_CPUACTLR_EL1, x0 48 isb 49 dsb ish 50 ret 51endfunc cortex_a72_disable_hw_prefetcher 52 53 /* --------------------------------------------- 54 * Disable intra-cluster coherency 55 * --------------------------------------------- 56 */ 57func cortex_a72_disable_smp 58 mrs x0, CORTEX_A72_ECTLR_EL1 59 bic x0, x0, #CORTEX_A72_ECTLR_SMP_BIT 60 msr CORTEX_A72_ECTLR_EL1, x0 61 ret 62endfunc cortex_a72_disable_smp 63 64 /* --------------------------------------------- 65 * Disable debug interfaces 66 * --------------------------------------------- 67 */ 68func cortex_a72_disable_ext_debug 69 mov x0, #1 70 msr osdlr_el1, x0 71 isb 72 dsb sy 73 ret 74endfunc cortex_a72_disable_ext_debug 75 76 /* -------------------------------------------------- 77 * Errata Workaround for Cortex A72 Errata #859971. 78 * This applies only to revision <= r0p3 of Cortex A72. 79 * Inputs: 80 * x0: variant[4:7] and revision[0:3] of current cpu. 81 * Shall clobber: 82 * -------------------------------------------------- 83 */ 84func errata_a72_859971_wa 85 mov x17,x30 86 bl check_errata_859971 87 cbz x0, 1f 88 mrs x1, CORTEX_A72_CPUACTLR_EL1 89 orr x1, x1, #CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH 90 msr CORTEX_A72_CPUACTLR_EL1, x1 911: 92 ret x17 93endfunc errata_a72_859971_wa 94 95func check_errata_859971 96 mov x1, #0x03 97 b cpu_rev_var_ls 98endfunc check_errata_859971 99 100func check_errata_cve_2017_5715 101#if WORKAROUND_CVE_2017_5715 102 mov x0, #ERRATA_APPLIES 103#else 104 mov x0, #ERRATA_MISSING 105#endif 106 ret 107endfunc check_errata_cve_2017_5715 108 109 /* ------------------------------------------------- 110 * The CPU Ops reset function for Cortex-A72. 111 * ------------------------------------------------- 112 */ 113func cortex_a72_reset_func 114 mov x19, x30 115 bl cpu_get_rev_var 116 mov x18, x0 117 118#if ERRATA_A72_859971 119 mov x0, x18 120 bl errata_a72_859971_wa 121#endif 122 123#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 124 adr x0, workaround_mmu_runtime_exceptions 125 msr vbar_el3, x0 126#endif 127 128 /* --------------------------------------------- 129 * Enable the SMP bit. 130 * --------------------------------------------- 131 */ 132 mrs x0, CORTEX_A72_ECTLR_EL1 133 orr x0, x0, #CORTEX_A72_ECTLR_SMP_BIT 134 msr CORTEX_A72_ECTLR_EL1, x0 135 isb 136 ret x19 137endfunc cortex_a72_reset_func 138 139 /* ---------------------------------------------------- 140 * The CPU Ops core power down function for Cortex-A72. 141 * ---------------------------------------------------- 142 */ 143func cortex_a72_core_pwr_dwn 144 mov x18, x30 145 146 /* --------------------------------------------- 147 * Turn off caches. 148 * --------------------------------------------- 149 */ 150 bl cortex_a72_disable_dcache 151 152 /* --------------------------------------------- 153 * Disable the L2 prefetches. 154 * --------------------------------------------- 155 */ 156 bl cortex_a72_disable_l2_prefetch 157 158 /* --------------------------------------------- 159 * Disable the load-store hardware prefetcher. 160 * --------------------------------------------- 161 */ 162 bl cortex_a72_disable_hw_prefetcher 163 164 /* --------------------------------------------- 165 * Flush L1 caches. 166 * --------------------------------------------- 167 */ 168 mov x0, #DCCISW 169 bl dcsw_op_level1 170 171 /* --------------------------------------------- 172 * Come out of intra cluster coherency 173 * --------------------------------------------- 174 */ 175 bl cortex_a72_disable_smp 176 177 /* --------------------------------------------- 178 * Force the debug interfaces to be quiescent 179 * --------------------------------------------- 180 */ 181 mov x30, x18 182 b cortex_a72_disable_ext_debug 183endfunc cortex_a72_core_pwr_dwn 184 185 /* ------------------------------------------------------- 186 * The CPU Ops cluster power down function for Cortex-A72. 187 * ------------------------------------------------------- 188 */ 189func cortex_a72_cluster_pwr_dwn 190 mov x18, x30 191 192 /* --------------------------------------------- 193 * Turn off caches. 194 * --------------------------------------------- 195 */ 196 bl cortex_a72_disable_dcache 197 198 /* --------------------------------------------- 199 * Disable the L2 prefetches. 200 * --------------------------------------------- 201 */ 202 bl cortex_a72_disable_l2_prefetch 203 204 /* --------------------------------------------- 205 * Disable the load-store hardware prefetcher. 206 * --------------------------------------------- 207 */ 208 bl cortex_a72_disable_hw_prefetcher 209 210#if !SKIP_A72_L1_FLUSH_PWR_DWN 211 /* --------------------------------------------- 212 * Flush L1 caches. 213 * --------------------------------------------- 214 */ 215 mov x0, #DCCISW 216 bl dcsw_op_level1 217#endif 218 219 /* --------------------------------------------- 220 * Disable the optional ACP. 221 * --------------------------------------------- 222 */ 223 bl plat_disable_acp 224 225 /* ------------------------------------------------- 226 * Flush the L2 caches. 227 * ------------------------------------------------- 228 */ 229 mov x0, #DCCISW 230 bl dcsw_op_level2 231 232 /* --------------------------------------------- 233 * Come out of intra cluster coherency 234 * --------------------------------------------- 235 */ 236 bl cortex_a72_disable_smp 237 238 /* --------------------------------------------- 239 * Force the debug interfaces to be quiescent 240 * --------------------------------------------- 241 */ 242 mov x30, x18 243 b cortex_a72_disable_ext_debug 244endfunc cortex_a72_cluster_pwr_dwn 245 246#if REPORT_ERRATA 247/* 248 * Errata printing function for Cortex A72. Must follow AAPCS. 249 */ 250func cortex_a72_errata_report 251 stp x8, x30, [sp, #-16]! 252 253 bl cpu_get_rev_var 254 mov x8, x0 255 256 /* 257 * Report all errata. The revision-variant information is passed to 258 * checking functions of each errata. 259 */ 260 report_errata ERRATA_A72_859971, cortex_a72, 859971 261 report_errata WORKAROUND_CVE_2017_5715, cortex_a72, cve_2017_5715 262 263 ldp x8, x30, [sp], #16 264 ret 265endfunc cortex_a72_errata_report 266#endif 267 268 /* --------------------------------------------- 269 * This function provides cortex_a72 specific 270 * register information for crash reporting. 271 * It needs to return with x6 pointing to 272 * a list of register names in ascii and 273 * x8 - x15 having values of registers to be 274 * reported. 275 * --------------------------------------------- 276 */ 277.section .rodata.cortex_a72_regs, "aS" 278cortex_a72_regs: /* The ascii list of register names to be reported */ 279 .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" 280 281func cortex_a72_cpu_reg_dump 282 adr x6, cortex_a72_regs 283 mrs x8, CORTEX_A72_ECTLR_EL1 284 mrs x9, CORTEX_A72_MERRSR_EL1 285 mrs x10, CORTEX_A72_L2MERRSR_EL1 286 ret 287endfunc cortex_a72_cpu_reg_dump 288 289 290declare_cpu_ops cortex_a72, CORTEX_A72_MIDR, \ 291 cortex_a72_reset_func, \ 292 cortex_a72_core_pwr_dwn, \ 293 cortex_a72_cluster_pwr_dwn 294