1/* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30#include <arch.h> 31#include <asm_macros.S> 32#include <assert_macros.S> 33#include <cortex_a72.h> 34#include <cpu_macros.S> 35#include <plat_macros.S> 36 37 /* --------------------------------------------- 38 * Disable L1 data cache and unified L2 cache 39 * --------------------------------------------- 40 */ 41func cortex_a72_disable_dcache 42 mrs x1, sctlr_el3 43 bic x1, x1, #SCTLR_C_BIT 44 msr sctlr_el3, x1 45 isb 46 ret 47endfunc cortex_a72_disable_dcache 48 49 /* --------------------------------------------- 50 * Disable all types of L2 prefetches. 51 * --------------------------------------------- 52 */ 53func cortex_a72_disable_l2_prefetch 54 mrs x0, CPUECTLR_EL1 55 orr x0, x0, #CPUECTLR_DIS_TWD_ACC_PFTCH_BIT 56 mov x1, #CPUECTLR_L2_IPFTCH_DIST_MASK 57 orr x1, x1, #CPUECTLR_L2_DPFTCH_DIST_MASK 58 bic x0, x0, x1 59 msr CPUECTLR_EL1, x0 60 isb 61 ret 62endfunc cortex_a72_disable_l2_prefetch 63 64 /* --------------------------------------------- 65 * Disable the load-store hardware prefetcher. 66 * --------------------------------------------- 67 */ 68func cortex_a72_disable_hw_prefetcher 69 mrs x0, CPUACTLR_EL1 70 orr x0, x0, #CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH 71 msr CPUACTLR_EL1, x0 72 isb 73 dsb ish 74 ret 75endfunc cortex_a72_disable_hw_prefetcher 76 77 /* --------------------------------------------- 78 * Disable intra-cluster coherency 79 * --------------------------------------------- 80 */ 81func cortex_a72_disable_smp 82 mrs x0, CPUECTLR_EL1 83 bic x0, x0, #CPUECTLR_SMP_BIT 84 msr CPUECTLR_EL1, x0 85 ret 86endfunc cortex_a72_disable_smp 87 88 /* --------------------------------------------- 89 * Disable debug interfaces 90 * --------------------------------------------- 91 */ 92func cortex_a72_disable_ext_debug 93 mov x0, #1 94 msr osdlr_el1, x0 95 isb 96 dsb sy 97 ret 98endfunc cortex_a72_disable_ext_debug 99 100 /* ------------------------------------------------- 101 * The CPU Ops reset function for Cortex-A72. 102 * ------------------------------------------------- 103 */ 104func cortex_a72_reset_func 105 /* --------------------------------------------- 106 * As a bare minimum enable the SMP bit. 107 * --------------------------------------------- 108 */ 109 mrs x0, CPUECTLR_EL1 110 orr x0, x0, #CPUECTLR_SMP_BIT 111 msr CPUECTLR_EL1, x0 112 isb 113 ret 114endfunc cortex_a72_reset_func 115 116 /* ---------------------------------------------------- 117 * The CPU Ops core power down function for Cortex-A72. 118 * ---------------------------------------------------- 119 */ 120func cortex_a72_core_pwr_dwn 121 mov x18, x30 122 123 /* --------------------------------------------- 124 * Turn off caches. 125 * --------------------------------------------- 126 */ 127 bl cortex_a72_disable_dcache 128 129 /* --------------------------------------------- 130 * Disable the L2 prefetches. 131 * --------------------------------------------- 132 */ 133 bl cortex_a72_disable_l2_prefetch 134 135 /* --------------------------------------------- 136 * Disable the load-store hardware prefetcher. 137 * --------------------------------------------- 138 */ 139 bl cortex_a72_disable_hw_prefetcher 140 141 /* --------------------------------------------- 142 * Flush L1 caches. 143 * --------------------------------------------- 144 */ 145 mov x0, #DCCISW 146 bl dcsw_op_level1 147 148 /* --------------------------------------------- 149 * Come out of intra cluster coherency 150 * --------------------------------------------- 151 */ 152 bl cortex_a72_disable_smp 153 154 /* --------------------------------------------- 155 * Force the debug interfaces to be quiescent 156 * --------------------------------------------- 157 */ 158 mov x30, x18 159 b cortex_a72_disable_ext_debug 160endfunc cortex_a72_core_pwr_dwn 161 162 /* ------------------------------------------------------- 163 * The CPU Ops cluster power down function for Cortex-A72. 164 * ------------------------------------------------------- 165 */ 166func cortex_a72_cluster_pwr_dwn 167 mov x18, x30 168 169 /* --------------------------------------------- 170 * Turn off caches. 171 * --------------------------------------------- 172 */ 173 bl cortex_a72_disable_dcache 174 175 /* --------------------------------------------- 176 * Disable the L2 prefetches. 177 * --------------------------------------------- 178 */ 179 bl cortex_a72_disable_l2_prefetch 180 181 /* --------------------------------------------- 182 * Disable the load-store hardware prefetcher. 183 * --------------------------------------------- 184 */ 185 bl cortex_a72_disable_hw_prefetcher 186 187#if !SKIP_A72_L1_FLUSH_PWR_DWN 188 /* --------------------------------------------- 189 * Flush L1 caches. 190 * --------------------------------------------- 191 */ 192 mov x0, #DCCISW 193 bl dcsw_op_level1 194#endif 195 196 /* --------------------------------------------- 197 * Disable the optional ACP. 198 * --------------------------------------------- 199 */ 200 bl plat_disable_acp 201 202 /* ------------------------------------------------- 203 * Flush the L2 caches. 204 * ------------------------------------------------- 205 */ 206 mov x0, #DCCISW 207 bl dcsw_op_level2 208 209 /* --------------------------------------------- 210 * Come out of intra cluster coherency 211 * --------------------------------------------- 212 */ 213 bl cortex_a72_disable_smp 214 215 /* --------------------------------------------- 216 * Force the debug interfaces to be quiescent 217 * --------------------------------------------- 218 */ 219 mov x30, x18 220 b cortex_a72_disable_ext_debug 221endfunc cortex_a72_cluster_pwr_dwn 222 223 /* --------------------------------------------- 224 * This function provides cortex_a72 specific 225 * register information for crash reporting. 226 * It needs to return with x6 pointing to 227 * a list of register names in ascii and 228 * x8 - x15 having values of registers to be 229 * reported. 230 * --------------------------------------------- 231 */ 232.section .rodata.cortex_a72_regs, "aS" 233cortex_a72_regs: /* The ascii list of register names to be reported */ 234 .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" 235 236func cortex_a72_cpu_reg_dump 237 adr x6, cortex_a72_regs 238 mrs x8, CPUECTLR_EL1 239 mrs x9, CPUMERRSR_EL1 240 mrs x10, L2MERRSR_EL1 241 ret 242endfunc cortex_a72_cpu_reg_dump 243 244 245declare_cpu_ops cortex_a72, CORTEX_A72_MIDR, \ 246 cortex_a72_reset_func, \ 247 cortex_a72_core_pwr_dwn, \ 248 cortex_a72_cluster_pwr_dwn 249