1/* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <assert_macros.S> 9#include <cortex_a72.h> 10#include <cpu_macros.S> 11#include <plat_macros.S> 12 13 /* --------------------------------------------- 14 * Disable L1 data cache and unified L2 cache 15 * --------------------------------------------- 16 */ 17func cortex_a72_disable_dcache 18 mrs x1, sctlr_el3 19 bic x1, x1, #SCTLR_C_BIT 20 msr sctlr_el3, x1 21 isb 22 ret 23endfunc cortex_a72_disable_dcache 24 25 /* --------------------------------------------- 26 * Disable all types of L2 prefetches. 27 * --------------------------------------------- 28 */ 29func cortex_a72_disable_l2_prefetch 30 mrs x0, CORTEX_A72_ECTLR_EL1 31 orr x0, x0, #CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT 32 mov x1, #CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK 33 orr x1, x1, #CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK 34 bic x0, x0, x1 35 msr CORTEX_A72_ECTLR_EL1, x0 36 isb 37 ret 38endfunc cortex_a72_disable_l2_prefetch 39 40 /* --------------------------------------------- 41 * Disable the load-store hardware prefetcher. 42 * --------------------------------------------- 43 */ 44func cortex_a72_disable_hw_prefetcher 45 mrs x0, CORTEX_A72_CPUACTLR_EL1 46 orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH 47 msr CORTEX_A72_CPUACTLR_EL1, x0 48 isb 49 dsb ish 50 ret 51endfunc cortex_a72_disable_hw_prefetcher 52 53 /* --------------------------------------------- 54 * Disable intra-cluster coherency 55 * --------------------------------------------- 56 */ 57func cortex_a72_disable_smp 58 mrs x0, CORTEX_A72_ECTLR_EL1 59 bic x0, x0, #CORTEX_A72_ECTLR_SMP_BIT 60 msr CORTEX_A72_ECTLR_EL1, x0 61 ret 62endfunc cortex_a72_disable_smp 63 64 /* --------------------------------------------- 65 * Disable debug interfaces 66 * --------------------------------------------- 67 */ 68func cortex_a72_disable_ext_debug 69 mov x0, #1 70 msr osdlr_el1, x0 71 isb 72 dsb sy 73 ret 74endfunc cortex_a72_disable_ext_debug 75 76 /* -------------------------------------------------- 77 * Errata Workaround for Cortex A72 Errata #859971. 78 * This applies only to revision <= r0p3 of Cortex A72. 79 * Inputs: 80 * x0: variant[4:7] and revision[0:3] of current cpu. 81 * Shall clobber: 82 * -------------------------------------------------- 83 */ 84func errata_a72_859971_wa 85 mov x17,x30 86 bl check_errata_859971 87 cbz x0, 1f 88 mrs x1, CORTEX_A72_CPUACTLR_EL1 89 orr x1, x1, #CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH 90 msr CORTEX_A72_CPUACTLR_EL1, x1 911: 92 ret x17 93endfunc errata_a72_859971_wa 94 95func check_errata_859971 96 mov x1, #0x03 97 b cpu_rev_var_ls 98endfunc check_errata_859971 99 100func check_errata_cve_2017_5715 101 cpu_check_csv2 x0, 1f 102#if WORKAROUND_CVE_2017_5715 103 mov x0, #ERRATA_APPLIES 104#else 105 mov x0, #ERRATA_MISSING 106#endif 107 ret 1081: 109 mov x0, #ERRATA_NOT_APPLIES 110 ret 111endfunc check_errata_cve_2017_5715 112 113 /* ------------------------------------------------- 114 * The CPU Ops reset function for Cortex-A72. 115 * ------------------------------------------------- 116 */ 117func cortex_a72_reset_func 118 mov x19, x30 119 bl cpu_get_rev_var 120 mov x18, x0 121 122#if ERRATA_A72_859971 123 mov x0, x18 124 bl errata_a72_859971_wa 125#endif 126 127#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 128 cpu_check_csv2 x0, 1f 129 adr x0, workaround_mmu_runtime_exceptions 130 msr vbar_el3, x0 1311: 132#endif 133 134 /* --------------------------------------------- 135 * Enable the SMP bit. 136 * --------------------------------------------- 137 */ 138 mrs x0, CORTEX_A72_ECTLR_EL1 139 orr x0, x0, #CORTEX_A72_ECTLR_SMP_BIT 140 msr CORTEX_A72_ECTLR_EL1, x0 141 isb 142 ret x19 143endfunc cortex_a72_reset_func 144 145 /* ---------------------------------------------------- 146 * The CPU Ops core power down function for Cortex-A72. 147 * ---------------------------------------------------- 148 */ 149func cortex_a72_core_pwr_dwn 150 mov x18, x30 151 152 /* --------------------------------------------- 153 * Turn off caches. 154 * --------------------------------------------- 155 */ 156 bl cortex_a72_disable_dcache 157 158 /* --------------------------------------------- 159 * Disable the L2 prefetches. 160 * --------------------------------------------- 161 */ 162 bl cortex_a72_disable_l2_prefetch 163 164 /* --------------------------------------------- 165 * Disable the load-store hardware prefetcher. 166 * --------------------------------------------- 167 */ 168 bl cortex_a72_disable_hw_prefetcher 169 170 /* --------------------------------------------- 171 * Flush L1 caches. 172 * --------------------------------------------- 173 */ 174 mov x0, #DCCISW 175 bl dcsw_op_level1 176 177 /* --------------------------------------------- 178 * Come out of intra cluster coherency 179 * --------------------------------------------- 180 */ 181 bl cortex_a72_disable_smp 182 183 /* --------------------------------------------- 184 * Force the debug interfaces to be quiescent 185 * --------------------------------------------- 186 */ 187 mov x30, x18 188 b cortex_a72_disable_ext_debug 189endfunc cortex_a72_core_pwr_dwn 190 191 /* ------------------------------------------------------- 192 * The CPU Ops cluster power down function for Cortex-A72. 193 * ------------------------------------------------------- 194 */ 195func cortex_a72_cluster_pwr_dwn 196 mov x18, x30 197 198 /* --------------------------------------------- 199 * Turn off caches. 200 * --------------------------------------------- 201 */ 202 bl cortex_a72_disable_dcache 203 204 /* --------------------------------------------- 205 * Disable the L2 prefetches. 206 * --------------------------------------------- 207 */ 208 bl cortex_a72_disable_l2_prefetch 209 210 /* --------------------------------------------- 211 * Disable the load-store hardware prefetcher. 212 * --------------------------------------------- 213 */ 214 bl cortex_a72_disable_hw_prefetcher 215 216#if !SKIP_A72_L1_FLUSH_PWR_DWN 217 /* --------------------------------------------- 218 * Flush L1 caches. 219 * --------------------------------------------- 220 */ 221 mov x0, #DCCISW 222 bl dcsw_op_level1 223#endif 224 225 /* --------------------------------------------- 226 * Disable the optional ACP. 227 * --------------------------------------------- 228 */ 229 bl plat_disable_acp 230 231 /* ------------------------------------------------- 232 * Flush the L2 caches. 233 * ------------------------------------------------- 234 */ 235 mov x0, #DCCISW 236 bl dcsw_op_level2 237 238 /* --------------------------------------------- 239 * Come out of intra cluster coherency 240 * --------------------------------------------- 241 */ 242 bl cortex_a72_disable_smp 243 244 /* --------------------------------------------- 245 * Force the debug interfaces to be quiescent 246 * --------------------------------------------- 247 */ 248 mov x30, x18 249 b cortex_a72_disable_ext_debug 250endfunc cortex_a72_cluster_pwr_dwn 251 252#if REPORT_ERRATA 253/* 254 * Errata printing function for Cortex A72. Must follow AAPCS. 255 */ 256func cortex_a72_errata_report 257 stp x8, x30, [sp, #-16]! 258 259 bl cpu_get_rev_var 260 mov x8, x0 261 262 /* 263 * Report all errata. The revision-variant information is passed to 264 * checking functions of each errata. 265 */ 266 report_errata ERRATA_A72_859971, cortex_a72, 859971 267 report_errata WORKAROUND_CVE_2017_5715, cortex_a72, cve_2017_5715 268 269 ldp x8, x30, [sp], #16 270 ret 271endfunc cortex_a72_errata_report 272#endif 273 274 /* --------------------------------------------- 275 * This function provides cortex_a72 specific 276 * register information for crash reporting. 277 * It needs to return with x6 pointing to 278 * a list of register names in ascii and 279 * x8 - x15 having values of registers to be 280 * reported. 281 * --------------------------------------------- 282 */ 283.section .rodata.cortex_a72_regs, "aS" 284cortex_a72_regs: /* The ascii list of register names to be reported */ 285 .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" 286 287func cortex_a72_cpu_reg_dump 288 adr x6, cortex_a72_regs 289 mrs x8, CORTEX_A72_ECTLR_EL1 290 mrs x9, CORTEX_A72_MERRSR_EL1 291 mrs x10, CORTEX_A72_L2MERRSR_EL1 292 ret 293endfunc cortex_a72_cpu_reg_dump 294 295declare_cpu_ops_workaround_cve_2017_5715 cortex_a72, CORTEX_A72_MIDR, \ 296 cortex_a72_reset_func, \ 297 check_errata_cve_2017_5715, \ 298 cortex_a72_core_pwr_dwn, \ 299 cortex_a72_cluster_pwr_dwn 300