1/* 2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <assert_macros.S> 9#include <cortex_a72.h> 10#include <cpu_macros.S> 11#include <plat_macros.S> 12#include "wa_cve_2022_23960_bhb_vector.S" 13 14#if WORKAROUND_CVE_2022_23960 15 wa_cve_2022_23960_bhb_vector_table CORTEX_A72_BHB_LOOP_COUNT, cortex_a72 16#endif /* WORKAROUND_CVE_2022_23960 */ 17 18cpu_reset_prologue cortex_a72 19 20 /* --------------------------------------------- 21 * Disable L1 data cache and unified L2 cache 22 * --------------------------------------------- 23 */ 24func cortex_a72_disable_dcache 25 mrs x1, sctlr_el3 26 bic x1, x1, #SCTLR_C_BIT 27 msr sctlr_el3, x1 28 isb 29 ret 30endfunc cortex_a72_disable_dcache 31 32 /* --------------------------------------------- 33 * Disable all types of L2 prefetches. 34 * --------------------------------------------- 35 */ 36func cortex_a72_disable_l2_prefetch 37 mrs x0, CORTEX_A72_ECTLR_EL1 38 orr x0, x0, #CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT 39 mov x1, #CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK 40 orr x1, x1, #CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK 41 bic x0, x0, x1 42 msr CORTEX_A72_ECTLR_EL1, x0 43 isb 44 ret 45endfunc cortex_a72_disable_l2_prefetch 46 47 /* --------------------------------------------- 48 * Disable the load-store hardware prefetcher. 49 * --------------------------------------------- 50 */ 51func cortex_a72_disable_hw_prefetcher 52 sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH 53 isb 54 dsb ish 55 ret 56endfunc cortex_a72_disable_hw_prefetcher 57 58 /* --------------------------------------------- 59 * Disable intra-cluster coherency 60 * --------------------------------------------- 61 */ 62func cortex_a72_disable_smp 63 sysreg_bit_clear CORTEX_A72_ECTLR_EL1, CORTEX_A72_ECTLR_SMP_BIT 64 ret 65endfunc cortex_a72_disable_smp 66 67 /* --------------------------------------------- 68 * Disable debug interfaces 69 * --------------------------------------------- 70 */ 71func cortex_a72_disable_ext_debug 72 mov x0, #1 73 msr osdlr_el1, x0 74 isb 75 dsb sy 76 ret 77endfunc cortex_a72_disable_ext_debug 78 79func check_smccc_arch_workaround_3 80 cpu_check_csv2 x0, 1f 81 mov x0, #ERRATA_APPLIES 82 ret 831: 84 mov x0, #ERRATA_NOT_APPLIES 85 ret 86endfunc check_smccc_arch_workaround_3 87 88workaround_reset_start cortex_a72, ERRATUM(859971), ERRATA_A72_859971 89 sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH 90workaround_reset_end cortex_a72, ERRATUM(859971) 91 92check_erratum_ls cortex_a72, ERRATUM(859971), CPU_REV(0, 3) 93 94/* Due to the nature of the errata it is applied unconditionally when chosen */ 95check_erratum_chosen cortex_a72, ERRATUM(1319367), ERRATA_A72_1319367 96/* erratum workaround is interleaved with generic code */ 97add_erratum_entry cortex_a72, ERRATUM(1319367), ERRATA_A72_1319367 98 99workaround_reset_start cortex_a72, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 100#if IMAGE_BL31 101 override_vector_table wa_cve_2017_5715_mmu_vbar 102#endif 103workaround_reset_end cortex_a72, CVE(2017, 5715) 104 105check_erratum_custom_start cortex_a72, CVE(2017, 5715) 106 cpu_check_csv2 x0, 1f 107#if WORKAROUND_CVE_2017_5715 108 mov x0, #ERRATA_APPLIES 109#else 110 mov x0, #ERRATA_MISSING 111#endif 112 ret 1131: 114 mov x0, #ERRATA_NOT_APPLIES 115 ret 116check_erratum_custom_end cortex_a72, CVE(2017, 5715) 117 118workaround_reset_start cortex_a72, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 119 sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE 120 isb 121 dsb sy 122workaround_reset_end cortex_a72, CVE(2018, 3639) 123check_erratum_chosen cortex_a72, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 124 125workaround_reset_start cortex_a72, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 126#if IMAGE_BL31 127 /* Skip installing vector table again if already done for CVE(2017, 5715) */ 128 /* 129 * The Cortex-A72 generic vectors are overridden to apply the 130 * mitigation on exception entry from lower ELs for revisions >= r1p0 131 * which has CSV2 implemented. 132 */ 133 adr x0, wa_cve_vbar_cortex_a72 134 mrs x1, vbar_el3 135 cmp x0, x1 136 b.eq 1f 137 msr vbar_el3, x0 1381: 139#endif /* IMAGE_BL31 */ 140workaround_reset_end cortex_a72, CVE(2022, 23960) 141 142check_erratum_custom_start cortex_a72, CVE(2022, 23960) 143#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 144 cpu_check_csv2 x0, 1f 145 mov x0, #ERRATA_APPLIES 146 ret 1471: 148#if WORKAROUND_CVE_2022_23960 149 mov x0, #ERRATA_APPLIES 150#else 151 mov x0, #ERRATA_MISSING 152#endif /* WORKAROUND_CVE_2022_23960 */ 153 ret 154#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */ 155 mov x0, #ERRATA_MISSING 156 ret 157check_erratum_custom_end cortex_a72, CVE(2022, 23960) 158 159cpu_reset_func_start cortex_a72 160 161 /* --------------------------------------------- 162 * Enable the SMP bit. 163 * --------------------------------------------- 164 */ 165 sysreg_bit_set CORTEX_A72_ECTLR_EL1, CORTEX_A72_ECTLR_SMP_BIT 166 167cpu_reset_func_end cortex_a72 168 169 /* ---------------------------------------------------- 170 * The CPU Ops core power down function for Cortex-A72. 171 * ---------------------------------------------------- 172 */ 173func cortex_a72_core_pwr_dwn 174 mov x18, x30 175 176 /* --------------------------------------------- 177 * Turn off caches. 178 * --------------------------------------------- 179 */ 180 bl cortex_a72_disable_dcache 181 182 /* --------------------------------------------- 183 * Disable the L2 prefetches. 184 * --------------------------------------------- 185 */ 186 bl cortex_a72_disable_l2_prefetch 187 188 /* --------------------------------------------- 189 * Disable the load-store hardware prefetcher. 190 * --------------------------------------------- 191 */ 192 bl cortex_a72_disable_hw_prefetcher 193 194 /* --------------------------------------------- 195 * Flush L1 caches. 196 * --------------------------------------------- 197 */ 198 mov x0, #DCCISW 199 bl dcsw_op_level1 200 201 /* --------------------------------------------- 202 * Come out of intra cluster coherency 203 * --------------------------------------------- 204 */ 205 bl cortex_a72_disable_smp 206 207 /* --------------------------------------------- 208 * Force the debug interfaces to be quiescent 209 * --------------------------------------------- 210 */ 211 mov x30, x18 212 b cortex_a72_disable_ext_debug 213endfunc cortex_a72_core_pwr_dwn 214 215 /* ------------------------------------------------------- 216 * The CPU Ops cluster power down function for Cortex-A72. 217 * ------------------------------------------------------- 218 */ 219func cortex_a72_cluster_pwr_dwn 220 mov x18, x30 221 222 /* --------------------------------------------- 223 * Turn off caches. 224 * --------------------------------------------- 225 */ 226 bl cortex_a72_disable_dcache 227 228 /* --------------------------------------------- 229 * Disable the L2 prefetches. 230 * --------------------------------------------- 231 */ 232 bl cortex_a72_disable_l2_prefetch 233 234 /* --------------------------------------------- 235 * Disable the load-store hardware prefetcher. 236 * --------------------------------------------- 237 */ 238 bl cortex_a72_disable_hw_prefetcher 239 240#if !SKIP_A72_L1_FLUSH_PWR_DWN 241 /* --------------------------------------------- 242 * Flush L1 caches. 243 * --------------------------------------------- 244 */ 245 mov x0, #DCCISW 246 bl dcsw_op_level1 247#endif 248 249 /* --------------------------------------------- 250 * Disable the optional ACP. 251 * --------------------------------------------- 252 */ 253 bl plat_disable_acp 254 255 /* ------------------------------------------------- 256 * Flush the L2 caches. 257 * ------------------------------------------------- 258 */ 259 mov x0, #DCCISW 260 bl dcsw_op_level2 261 262 /* --------------------------------------------- 263 * Come out of intra cluster coherency 264 * --------------------------------------------- 265 */ 266 bl cortex_a72_disable_smp 267 268 /* --------------------------------------------- 269 * Force the debug interfaces to be quiescent 270 * --------------------------------------------- 271 */ 272 mov x30, x18 273 b cortex_a72_disable_ext_debug 274endfunc cortex_a72_cluster_pwr_dwn 275 276 /* --------------------------------------------- 277 * This function provides cortex_a72 specific 278 * register information for crash reporting. 279 * It needs to return with x6 pointing to 280 * a list of register names in ascii and 281 * x8 - x15 having values of registers to be 282 * reported. 283 * --------------------------------------------- 284 */ 285.section .rodata.cortex_a72_regs, "aS" 286cortex_a72_regs: /* The ascii list of register names to be reported */ 287 .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" 288 289func cortex_a72_cpu_reg_dump 290 adr x6, cortex_a72_regs 291 mrs x8, CORTEX_A72_ECTLR_EL1 292 mrs x9, CORTEX_A72_MERRSR_EL1 293 mrs x10, CORTEX_A72_L2MERRSR_EL1 294 ret 295endfunc cortex_a72_cpu_reg_dump 296 297declare_cpu_ops_wa cortex_a72, CORTEX_A72_MIDR, \ 298 cortex_a72_reset_func, \ 299 check_erratum_cortex_a72_5715, \ 300 CPU_NO_EXTRA2_FUNC, \ 301 check_smccc_arch_workaround_3, \ 302 cortex_a72_core_pwr_dwn, \ 303 cortex_a72_cluster_pwr_dwn 304