1/* 2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <assert_macros.S> 9#include <cortex_a72.h> 10#include <cpu_macros.S> 11#include <plat_macros.S> 12#include "wa_cve_2022_23960_bhb_vector.S" 13 14#if WORKAROUND_CVE_2022_23960 15 wa_cve_2022_23960_bhb_vector_table CORTEX_A72_BHB_LOOP_COUNT, cortex_a72 16#endif /* WORKAROUND_CVE_2022_23960 */ 17 18cpu_reset_prologue cortex_a72 19 20 /* --------------------------------------------- 21 * Disable L1 data cache and unified L2 cache 22 * --------------------------------------------- 23 */ 24func cortex_a72_disable_dcache 25 mrs x1, sctlr_el3 26 bic x1, x1, #SCTLR_C_BIT 27 msr sctlr_el3, x1 28 isb 29 ret 30endfunc cortex_a72_disable_dcache 31 32 /* --------------------------------------------- 33 * Disable all types of L2 prefetches. 34 * --------------------------------------------- 35 */ 36func cortex_a72_disable_l2_prefetch 37 mrs x0, CORTEX_A72_ECTLR_EL1 38 orr x0, x0, #CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT 39 mov x1, #CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK 40 orr x1, x1, #CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK 41 bic x0, x0, x1 42 msr CORTEX_A72_ECTLR_EL1, x0 43 isb 44 ret 45endfunc cortex_a72_disable_l2_prefetch 46 47 /* --------------------------------------------- 48 * Disable the load-store hardware prefetcher. 49 * --------------------------------------------- 50 */ 51func cortex_a72_disable_hw_prefetcher 52 sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH 53 isb 54 dsb ish 55 ret 56endfunc cortex_a72_disable_hw_prefetcher 57 58 /* --------------------------------------------- 59 * Disable intra-cluster coherency 60 * --------------------------------------------- 61 */ 62func cortex_a72_disable_smp 63 sysreg_bit_clear CORTEX_A72_ECTLR_EL1, CORTEX_A72_ECTLR_SMP_BIT 64 ret 65endfunc cortex_a72_disable_smp 66 67 /* --------------------------------------------- 68 * Disable debug interfaces 69 * --------------------------------------------- 70 */ 71func cortex_a72_disable_ext_debug 72 mov x0, #1 73 msr osdlr_el1, x0 74 isb 75 dsb sy 76 ret 77endfunc cortex_a72_disable_ext_debug 78 79check_erratum_custom_start cortex_a72, ERRATUM(ARCH_WORKAROUND_3) 80 cpu_check_csv2 x0, 1f 81 mov x0, #ERRATA_APPLIES 82 ret 831: 84 mov x0, #ERRATA_NOT_APPLIES 85 ret 86check_erratum_custom_end cortex_a72, ERRATUM(ARCH_WORKAROUND_3) 87 88/* Erratum entry and check function for SMCCC_ARCH_WORKAROUND_3 */ 89add_erratum_entry cortex_a72, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960 90 91workaround_reset_start cortex_a72, ERRATUM(859971), ERRATA_A72_859971 92 sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH 93workaround_reset_end cortex_a72, ERRATUM(859971) 94 95check_erratum_ls cortex_a72, ERRATUM(859971), CPU_REV(0, 3) 96 97/* Due to the nature of the errata it is applied unconditionally when chosen */ 98check_erratum_chosen cortex_a72, ERRATUM(1319367), ERRATA_A72_1319367 99/* erratum workaround is interleaved with generic code */ 100add_erratum_entry cortex_a72, ERRATUM(1319367), ERRATA_A72_1319367 101 102workaround_reset_start cortex_a72, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 103#if IMAGE_BL31 104 override_vector_table wa_cve_2017_5715_mmu_vbar 105#endif 106workaround_reset_end cortex_a72, CVE(2017, 5715) 107 108check_erratum_custom_start cortex_a72, CVE(2017, 5715) 109 cpu_check_csv2 x0, 1f 110#if WORKAROUND_CVE_2017_5715 111 mov x0, #ERRATA_APPLIES 112#else 113 mov x0, #ERRATA_MISSING 114#endif 115 ret 1161: 117 mov x0, #ERRATA_NOT_APPLIES 118 ret 119check_erratum_custom_end cortex_a72, CVE(2017, 5715) 120 121workaround_reset_start cortex_a72, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 122 sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE 123 isb 124 dsb sy 125workaround_reset_end cortex_a72, CVE(2018, 3639) 126check_erratum_chosen cortex_a72, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 127 128workaround_reset_start cortex_a72, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 129#if IMAGE_BL31 130 /* Skip installing vector table again if already done for CVE(2017, 5715) */ 131 /* 132 * The Cortex-A72 generic vectors are overridden to apply the 133 * mitigation on exception entry from lower ELs for revisions >= r1p0 134 * which has CSV2 implemented. 135 */ 136 adr x0, wa_cve_vbar_cortex_a72 137 mrs x1, vbar_el3 138 cmp x0, x1 139 b.eq 1f 140 msr vbar_el3, x0 1411: 142#endif /* IMAGE_BL31 */ 143workaround_reset_end cortex_a72, CVE(2022, 23960) 144 145check_erratum_custom_start cortex_a72, CVE(2022, 23960) 146#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 147 cpu_check_csv2 x0, 1f 148 mov x0, #ERRATA_APPLIES 149 ret 1501: 151#if WORKAROUND_CVE_2022_23960 152 mov x0, #ERRATA_APPLIES 153#else 154 mov x0, #ERRATA_MISSING 155#endif /* WORKAROUND_CVE_2022_23960 */ 156 ret 157#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */ 158 mov x0, #ERRATA_MISSING 159 ret 160check_erratum_custom_end cortex_a72, CVE(2022, 23960) 161 162cpu_reset_func_start cortex_a72 163 164 /* --------------------------------------------- 165 * Enable the SMP bit. 166 * --------------------------------------------- 167 */ 168 sysreg_bit_set CORTEX_A72_ECTLR_EL1, CORTEX_A72_ECTLR_SMP_BIT 169 170cpu_reset_func_end cortex_a72 171 172 /* ---------------------------------------------------- 173 * The CPU Ops core power down function for Cortex-A72. 174 * ---------------------------------------------------- 175 */ 176func cortex_a72_core_pwr_dwn 177 mov x18, x30 178 179 /* --------------------------------------------- 180 * Turn off caches. 181 * --------------------------------------------- 182 */ 183 bl cortex_a72_disable_dcache 184 185 /* --------------------------------------------- 186 * Disable the L2 prefetches. 187 * --------------------------------------------- 188 */ 189 bl cortex_a72_disable_l2_prefetch 190 191 /* --------------------------------------------- 192 * Disable the load-store hardware prefetcher. 193 * --------------------------------------------- 194 */ 195 bl cortex_a72_disable_hw_prefetcher 196 197 /* --------------------------------------------- 198 * Flush L1 caches. 199 * --------------------------------------------- 200 */ 201 mov x0, #DCCISW 202 bl dcsw_op_level1 203 204 /* --------------------------------------------- 205 * Come out of intra cluster coherency 206 * --------------------------------------------- 207 */ 208 bl cortex_a72_disable_smp 209 210 /* --------------------------------------------- 211 * Force the debug interfaces to be quiescent 212 * --------------------------------------------- 213 */ 214 mov x30, x18 215 b cortex_a72_disable_ext_debug 216endfunc cortex_a72_core_pwr_dwn 217 218 /* ------------------------------------------------------- 219 * The CPU Ops cluster power down function for Cortex-A72. 220 * ------------------------------------------------------- 221 */ 222func cortex_a72_cluster_pwr_dwn 223 mov x18, x30 224 225 /* --------------------------------------------- 226 * Turn off caches. 227 * --------------------------------------------- 228 */ 229 bl cortex_a72_disable_dcache 230 231 /* --------------------------------------------- 232 * Disable the L2 prefetches. 233 * --------------------------------------------- 234 */ 235 bl cortex_a72_disable_l2_prefetch 236 237 /* --------------------------------------------- 238 * Disable the load-store hardware prefetcher. 239 * --------------------------------------------- 240 */ 241 bl cortex_a72_disable_hw_prefetcher 242 243#if !SKIP_A72_L1_FLUSH_PWR_DWN 244 /* --------------------------------------------- 245 * Flush L1 caches. 246 * --------------------------------------------- 247 */ 248 mov x0, #DCCISW 249 bl dcsw_op_level1 250#endif 251 252 /* --------------------------------------------- 253 * Disable the optional ACP. 254 * --------------------------------------------- 255 */ 256 bl plat_disable_acp 257 258 /* ------------------------------------------------- 259 * Flush the L2 caches. 260 * ------------------------------------------------- 261 */ 262 mov x0, #DCCISW 263 bl dcsw_op_level2 264 265 /* --------------------------------------------- 266 * Come out of intra cluster coherency 267 * --------------------------------------------- 268 */ 269 bl cortex_a72_disable_smp 270 271 /* --------------------------------------------- 272 * Force the debug interfaces to be quiescent 273 * --------------------------------------------- 274 */ 275 mov x30, x18 276 b cortex_a72_disable_ext_debug 277endfunc cortex_a72_cluster_pwr_dwn 278 279 /* --------------------------------------------- 280 * This function provides cortex_a72 specific 281 * register information for crash reporting. 282 * It needs to return with x6 pointing to 283 * a list of register names in ascii and 284 * x8 - x15 having values of registers to be 285 * reported. 286 * --------------------------------------------- 287 */ 288.section .rodata.cortex_a72_regs, "aS" 289cortex_a72_regs: /* The ascii list of register names to be reported */ 290 .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" 291 292func cortex_a72_cpu_reg_dump 293 adr x6, cortex_a72_regs 294 mrs x8, CORTEX_A72_ECTLR_EL1 295 mrs x9, CORTEX_A72_MERRSR_EL1 296 mrs x10, CORTEX_A72_L2MERRSR_EL1 297 ret 298endfunc cortex_a72_cpu_reg_dump 299 300declare_cpu_ops cortex_a72, CORTEX_A72_MIDR, \ 301 cortex_a72_reset_func, \ 302 cortex_a72_core_pwr_dwn, \ 303 cortex_a72_cluster_pwr_dwn 304