1/* 2 * Copyright (c) 2021-2026, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a715.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-A715 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-A715 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25.global check_erratum_cortex_a715_3699560 26 27#if WORKAROUND_CVE_2022_23960 28 wa_cve_2022_23960_bhb_vector_table CORTEX_A715_BHB_LOOP_COUNT, cortex_a715 29#endif /* WORKAROUND_CVE_2022_23960 */ 30 31cpu_reset_prologue cortex_a715 32 33workaround_reset_start cortex_a715, ERRATUM(2238661), ERRATA_A715_2238661 34 sysreg_bit_set CORTEX_A715_CPUACTLR_EL1, BIT(0) 35workaround_reset_end cortex_a715, ERRATUM(2238661) 36 37check_erratum_ls cortex_a715, ERRATUM(2238661), CPU_REV(0, 0) 38 39workaround_reset_start cortex_a715, ERRATUM(2239006), ERRATA_A715_2239006 40 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(9) 41workaround_reset_end cortex_a715, ERRATUM(2239006) 42 43check_erratum_ls cortex_a715, ERRATUM(2239006), CPU_REV(0, 0) 44 45workaround_reset_start cortex_a715, ERRATUM(2275754), ERRATA_A715_2275754 46 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(20) 47workaround_reset_end cortex_a715, ERRATUM(2275754) 48 49check_erratum_ls cortex_a715, ERRATUM(2275754), CPU_REV(0, 0) 50 51workaround_reset_start cortex_a715, ERRATUM(2284544), ERRATA_A715_2284544 52 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(20) 53workaround_reset_end cortex_a715, ERRATUM(2284544) 54 55check_erratum_ls cortex_a715, ERRATUM(2284544), CPU_REV(0, 0) 56 57workaround_reset_start cortex_a715, ERRATUM(2285473), ERRATA_A715_2285473 58 sysreg_bit_set CORTEX_A715_CPUACTLR3_EL1, BIT(12) 59workaround_reset_end cortex_a715, ERRATUM(2285473) 60 61check_erratum_ls cortex_a715, ERRATUM(2285473), CPU_REV(0, 0) 62 63workaround_reset_start cortex_a715, ERRATUM(2292761), ERRATA_A715_2292761 64 sysreg_bit_set CORTEX_A715_CPUACTLR4_EL1, BIT(13) 65workaround_reset_end cortex_a715, ERRATUM(2292761) 66 67check_erratum_ls cortex_a715, ERRATUM(2292761), CPU_REV(0, 0) 68 69workaround_reset_start cortex_a715, ERRATUM(2331818), ERRATA_A715_2331818 70 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(20) 71workaround_reset_end cortex_a715, ERRATUM(2331818) 72 73check_erratum_ls cortex_a715, ERRATUM(2331818), CPU_REV(1, 0) 74 75workaround_reset_start cortex_a715, ERRATUM(2344187), ERRATA_A715_2344187 76 /* GCR_EL1 is only present with FEAT_MTE2. */ 77 mrs x1, ID_AA64PFR1_EL1 78 ubfx x0, x1, ID_AA64PFR1_EL1_MTE_SHIFT, #4 79 cmp x0, #MTE_IMPLEMENTED_ELX 80 bne #1f 81 sysreg_bit_set GCR_EL1, GCR_EL1_RRND_BIT 82 831: 84 /* Mitigation upon ERETAA and ERETAB. */ 85 mov x0, #2 86 msr CORTEX_A715_CPUPSELR_EL3, x0 87 isb 88 ldr x0, =0xd69f0bff 89 msr CORTEX_A715_CPUPOR_EL3, x0 90 ldr x0, =0xfffffbff 91 msr CORTEX_A715_CPUPMR_EL3, x0 92 mov x1, #0 93 orr x1, x1, #(1<<0) 94 orr x1, x1, #(3<<4) 95 orr x1, x1, #(0xf<<6) 96 orr x1, x1, #(1<<13) 97 orr x1, x1, #(1<<53) 98 msr CORTEX_A715_CPUPCR_EL3, x1 99workaround_reset_end cortex_a715, ERRATUM(2344187) 100 101check_erratum_ls cortex_a715, ERRATUM(2344187), CPU_REV(1, 0) 102 103workaround_reset_start cortex_a715, ERRATUM(2376701), ERRATA_A715_2376701 104sysreg_bit_set CORTEX_A715_CPUACTLR_EL1, BIT(0) 105workaround_reset_end cortex_a715, ERRATUM(2376701) 106 107check_erratum_ls cortex_a715, ERRATUM(2376701), CPU_REV(1, 0) 108 109workaround_reset_start cortex_a715, ERRATUM(2409570), ERRATA_A715_2409570 110sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(32) 111workaround_reset_end cortex_a715, ERRATUM(2409570) 112 113check_erratum_range cortex_a715, ERRATUM(2409570), CPU_REV(1, 0), CPU_REV(1, 0) 114 115workaround_reset_start cortex_a715, ERRATUM(2413290), ERRATA_A715_2413290 116/* Erratum 2413290 workaround is required only if SPE is enabled */ 117#if ENABLE_SPE_FOR_NS != 0 118 /* Check if Static profiling extension is implemented or present. */ 119 mrs x1, id_aa64dfr0_el1 120 ubfx x0, x1, ID_AA64DFR0_PMS_SHIFT, #4 121 cbz x0, 1f 122 /* Apply the workaround by setting CPUACTLR_EL1[58:57] = 0b11. */ 123 sysreg_bit_set CORTEX_A715_CPUACTLR_EL1, BIT(57) 124 sysreg_bit_set CORTEX_A715_CPUACTLR_EL1, BIT(58) 1251: 126#endif 127workaround_reset_end cortex_a715, ERRATUM(2413290) 128 129check_erratum_range cortex_a715, ERRATUM(2413290), CPU_REV(1,0), CPU_REV(1, 0) 130 131workaround_reset_start cortex_a715, ERRATUM(2420947), ERRATA_A715_2420947 132 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(33) 133workaround_reset_end cortex_a715, ERRATUM(2420947) 134 135check_erratum_range cortex_a715, ERRATUM(2420947), CPU_REV(1, 0), CPU_REV(1, 0) 136 137workaround_reset_start cortex_a715, ERRATUM(2429384), ERRATA_A715_2429384 138 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(27) 139workaround_reset_end cortex_a715, ERRATUM(2429384) 140 141check_erratum_range cortex_a715, ERRATUM(2429384), CPU_REV(1, 0), CPU_REV(1, 0) 142 143workaround_reset_start cortex_a715, ERRATUM(2561034), ERRATA_A715_2561034 144 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(26) 145workaround_reset_end cortex_a715, ERRATUM(2561034) 146 147check_erratum_range cortex_a715, ERRATUM(2561034), CPU_REV(1, 0), CPU_REV(1, 0) 148 149workaround_reset_start cortex_a715, ERRATUM(2728106), ERRATA_A715_2728106 150 mov x0, #3 151 msr CORTEX_A715_CPUPSELR_EL3, x0 152 isb 153 ldr x0, =0xd503339f 154 msr CORTEX_A715_CPUPOR_EL3, x0 155 ldr x0, =0xfffff3ff 156 msr CORTEX_A715_CPUPMR_EL3, x0 157 mov x0, #1 158 orr x0, x0, #(3<<4) 159 orr x0, x0, #(0xf<<6) 160 orr x0, x0, #(1<<13) 161 orr x0, x0, #(1<<20) 162 orr x0, x0, #(1<<22) 163 orr x0, x0, #(1<<31) 164 orr x0, x0, #(1<<50) 165 msr CORTEX_A715_CPUPCR_EL3, x0 166workaround_reset_end cortex_a715, ERRATUM(2728106) 167 168check_erratum_ls cortex_a715, ERRATUM(2728106), CPU_REV(1, 1) 169 170workaround_reset_start cortex_a715, ERRATUM(2804830), ERRATA_A715_2804830 171 /* Workaround changes based on CORE_CACHE_PROTECTIONS field (bit 1) */ 172 mrs x0, CORTEX_A715_CPUCFR_EL1 173 tbz x0, #1, wa_2804830_core_cache_prot_false 174 175 /* CORE_CACHE_PROTECTIONS==true */ 176 sysreg_bit_set CORTEX_A715_CPUACTLR3_EL1, BIT(2) 177 sysreg_bit_set CORTEX_A715_CPUECTLR_EL1, BIT(23) 178 b wa_2804830_done 179 180 /* CORE_CACHE_PROTECTIONS==false */ 181wa_2804830_core_cache_prot_false: 182 sysreg_bit_set CORTEX_A715_CPUECTLR2_EL1, BIT(7) 183 184wa_2804830_done: 185workaround_reset_end cortex_a715, ERRATUM(2804830) 186 187check_erratum_ls cortex_a715, ERRATUM(2804830), CPU_REV(1, 2) 188 189workaround_runtime_start cortex_a715, ERRATUM(3456084), ERRATA_A715_3456084 190 speculation_barrier 191workaround_runtime_end cortex_a715, ERRATUM(3456084) 192 193check_erratum_ls cortex_a715, ERRATUM(3456084), CPU_REV(1, 3) 194 195add_erratum_entry cortex_a715, ERRATUM(3699560), ERRATA_A715_3699560 196 197check_erratum_ls cortex_a715, ERRATUM(3699560), CPU_REV(1, 3) 198 199workaround_reset_start cortex_a715, ERRATUM(3711916), ERRATA_A715_3711916 200 mov x0, #5 201 msr CORTEX_A715_CPUPSELR_EL3, x0 202 ldr x0, =0xd503329f 203 msr CORTEX_A715_CPUPOR_EL3, x0 204 ldr x0, =0xfffff3ff 205 msr CORTEX_A715_CPUPMR_EL3, x0 206 ldr x0, =0x1004003F1 207 msr CORTEX_A715_CPUPCR_EL3, x0 208workaround_reset_end cortex_a715, ERRATUM(3711916) 209 210check_erratum_ls cortex_a715, ERRATUM(3711916), CPU_REV(1, 3) 211 212workaround_reset_start cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 213#if IMAGE_BL31 214 /* 215 * The Cortex-A715 generic vectors are overridden to apply errata 216 * mitigation on exception entry from lower ELs. 217 */ 218 override_vector_table wa_cve_vbar_cortex_a715 219#endif /* IMAGE_BL31 */ 220workaround_reset_end cortex_a715, CVE(2022, 23960) 221 222check_erratum_ls cortex_a715, CVE(2022, 23960), CPU_REV(1, 0) 223 224cpu_reset_func_start cortex_a715 225 /* Disable speculative loads */ 226 msr SSBS, xzr 227 apply_erratum cortex_a715, ERRATUM(3456084), ERRATA_A715_3456084 228 229 enable_mpmm 230cpu_reset_func_end cortex_a715 231 232 /* ---------------------------------------------------- 233 * HW will do the cache maintenance while powering down 234 * ---------------------------------------------------- 235 */ 236func cortex_a715_core_pwr_dwn 237 /* --------------------------------------------------- 238 * Enable CPU power down bit in power control register 239 * --------------------------------------------------- 240 */ 241 mrs x0, CORTEX_A715_CPUPWRCTLR_EL1 242 orr x0, x0, #CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 243 msr CORTEX_A715_CPUPWRCTLR_EL1, x0 244 isb 245 ret 246endfunc cortex_a715_core_pwr_dwn 247 248 /* --------------------------------------------- 249 * This function provides Cortex-A715 specific 250 * register information for crash reporting. 251 * It needs to return with x6 pointing to 252 * a list of register names in ascii and 253 * x8 - x15 having values of registers to be 254 * reported. 255 * --------------------------------------------- 256 */ 257.section .rodata.cortex_a715_regs, "aS" 258cortex_a715_regs: /* The ascii list of register names to be reported */ 259 .asciz "cpuectlr_el1", "" 260 261func cortex_a715_cpu_reg_dump 262 adr x6, cortex_a715_regs 263 mrs x8, CORTEX_A715_CPUECTLR_EL1 264 ret 265endfunc cortex_a715_cpu_reg_dump 266 267declare_cpu_ops cortex_a715, CORTEX_A715_MIDR, \ 268 cortex_a715_reset_func, \ 269 cortex_a715_core_pwr_dwn 270