1/* 2 * Copyright (c) 2021-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a715.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-A715 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-A715 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_A715_BHB_LOOP_COUNT, cortex_a715 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29workaround_reset_start cortex_a715, ERRATUM(2331818), ERRATA_A715_2331818 30 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(20) 31workaround_reset_end cortex_a715, ERRATUM(2331818) 32 33check_erratum_ls cortex_a715, ERRATUM(2331818), CPU_REV(1, 0) 34 35workaround_reset_start cortex_a715, ERRATUM(2420947), ERRATA_A715_2420947 36 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(33) 37workaround_reset_end cortex_a715, ERRATUM(2420947) 38 39check_erratum_range cortex_a715, ERRATUM(2420947), CPU_REV(1, 0), CPU_REV(1, 0) 40 41workaround_reset_start cortex_a715, ERRATUM(2429384), ERRATA_A715_2429384 42 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(27) 43workaround_reset_end cortex_a715, ERRATUM(2429384) 44 45check_erratum_range cortex_a715, ERRATUM(2429384), CPU_REV(1, 0), CPU_REV(1, 0) 46 47workaround_runtime_start cortex_a715, ERRATUM(2561034), ERRATA_A715_2561034 48 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(26) 49workaround_runtime_end cortex_a715, ERRATUM(2561034), NO_ISB 50 51check_erratum_range cortex_a715, ERRATUM(2561034), CPU_REV(1, 0), CPU_REV(1, 0) 52 53workaround_reset_start cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 54#if IMAGE_BL31 55 /* 56 * The Cortex-A715 generic vectors are overridden to apply errata 57 * mitigation on exception entry from lower ELs. 58 */ 59 override_vector_table wa_cve_vbar_cortex_a715 60#endif /* IMAGE_BL31 */ 61workaround_reset_end cortex_a715, CVE(2022, 23960) 62 63check_erratum_chosen cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 64 65cpu_reset_func_start cortex_a715 66 /* Disable speculative loads */ 67 msr SSBS, xzr 68cpu_reset_func_end cortex_a715 69 70 /* ---------------------------------------------------- 71 * HW will do the cache maintenance while powering down 72 * ---------------------------------------------------- 73 */ 74func cortex_a715_core_pwr_dwn 75 /* --------------------------------------------------- 76 * Enable CPU power down bit in power control register 77 * --------------------------------------------------- 78 */ 79 mrs x0, CORTEX_A715_CPUPWRCTLR_EL1 80 orr x0, x0, #CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 81 msr CORTEX_A715_CPUPWRCTLR_EL1, x0 82 isb 83 ret 84endfunc cortex_a715_core_pwr_dwn 85 86errata_report_shim cortex_a715 87 88 /* --------------------------------------------- 89 * This function provides Cortex-A715 specific 90 * register information for crash reporting. 91 * It needs to return with x6 pointing to 92 * a list of register names in ascii and 93 * x8 - x15 having values of registers to be 94 * reported. 95 * --------------------------------------------- 96 */ 97.section .rodata.cortex_a715_regs, "aS" 98cortex_a715_regs: /* The ascii list of register names to be reported */ 99 .asciz "cpuectlr_el1", "" 100 101func cortex_a715_cpu_reg_dump 102 adr x6, cortex_a715_regs 103 mrs x8, CORTEX_A715_CPUECTLR_EL1 104 ret 105endfunc cortex_a715_cpu_reg_dump 106 107declare_cpu_ops cortex_a715, CORTEX_A715_MIDR, \ 108 cortex_a715_reset_func, \ 109 cortex_a715_core_pwr_dwn 110