1/* 2 * Copyright (c) 2021-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a715.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-A715 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-A715 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_A715_BHB_LOOP_COUNT, cortex_a715 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29workaround_reset_start cortex_a715, ERRATUM(2429384), ERRATA_A715_2429384 30 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(27) 31workaround_reset_end cortex_a715, ERRATUM(2429384) 32 33check_erratum_range cortex_a715, ERRATUM(2429384), CPU_REV(1, 0), CPU_REV(1, 0) 34 35workaround_runtime_start cortex_a715, ERRATUM(2561034), ERRATA_A715_2561034 36 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(26) 37workaround_runtime_end cortex_a715, ERRATUM(2561034), NO_ISB 38 39check_erratum_range cortex_a715, ERRATUM(2561034), CPU_REV(1, 0), CPU_REV(1, 0) 40 41workaround_reset_start cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 42#if IMAGE_BL31 43 /* 44 * The Cortex-A715 generic vectors are overridden to apply errata 45 * mitigation on exception entry from lower ELs. 46 */ 47 override_vector_table wa_cve_vbar_cortex_a715 48#endif /* IMAGE_BL31 */ 49workaround_reset_end cortex_a715, CVE(2022, 23960) 50 51check_erratum_chosen cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 52 53cpu_reset_func_start cortex_a715 54 /* Disable speculative loads */ 55 msr SSBS, xzr 56cpu_reset_func_end cortex_a715 57 58 /* ---------------------------------------------------- 59 * HW will do the cache maintenance while powering down 60 * ---------------------------------------------------- 61 */ 62func cortex_a715_core_pwr_dwn 63 /* --------------------------------------------------- 64 * Enable CPU power down bit in power control register 65 * --------------------------------------------------- 66 */ 67 mrs x0, CORTEX_A715_CPUPWRCTLR_EL1 68 orr x0, x0, #CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 69 msr CORTEX_A715_CPUPWRCTLR_EL1, x0 70 isb 71 ret 72endfunc cortex_a715_core_pwr_dwn 73 74errata_report_shim cortex_a715 75 76 /* --------------------------------------------- 77 * This function provides Cortex-A715 specific 78 * register information for crash reporting. 79 * It needs to return with x6 pointing to 80 * a list of register names in ascii and 81 * x8 - x15 having values of registers to be 82 * reported. 83 * --------------------------------------------- 84 */ 85.section .rodata.cortex_a715_regs, "aS" 86cortex_a715_regs: /* The ascii list of register names to be reported */ 87 .asciz "cpuectlr_el1", "" 88 89func cortex_a715_cpu_reg_dump 90 adr x6, cortex_a715_regs 91 mrs x8, CORTEX_A715_CPUECTLR_EL1 92 ret 93endfunc cortex_a715_cpu_reg_dump 94 95declare_cpu_ops cortex_a715, CORTEX_A715_MIDR, \ 96 cortex_a715_reset_func, \ 97 cortex_a715_core_pwr_dwn 98