1/* 2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a715.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-A715 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-A715 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_A715_BHB_LOOP_COUNT, cortex_a715 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29workaround_reset_start cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 30#if IMAGE_BL31 31 /* 32 * The Cortex-A715 generic vectors are overridden to apply errata 33 * mitigation on exception entry from lower ELs. 34 */ 35 override_vector_table wa_cve_vbar_cortex_a715 36#endif /* IMAGE_BL31 */ 37workaround_reset_end cortex_a715, CVE(2022, 23960) 38 39check_erratum_chosen cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 40 41cpu_reset_func_start cortex_a715 42 /* Disable speculative loads */ 43 msr SSBS, xzr 44cpu_reset_func_end cortex_a715 45 46 /* ---------------------------------------------------- 47 * HW will do the cache maintenance while powering down 48 * ---------------------------------------------------- 49 */ 50func cortex_a715_core_pwr_dwn 51 /* --------------------------------------------------- 52 * Enable CPU power down bit in power control register 53 * --------------------------------------------------- 54 */ 55 mrs x0, CORTEX_A715_CPUPWRCTLR_EL1 56 orr x0, x0, #CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 57 msr CORTEX_A715_CPUPWRCTLR_EL1, x0 58 isb 59 ret 60endfunc cortex_a715_core_pwr_dwn 61 62errata_report_shim cortex_a715 63 64 /* --------------------------------------------- 65 * This function provides Cortex-A715 specific 66 * register information for crash reporting. 67 * It needs to return with x6 pointing to 68 * a list of register names in ascii and 69 * x8 - x15 having values of registers to be 70 * reported. 71 * --------------------------------------------- 72 */ 73.section .rodata.cortex_a715_regs, "aS" 74cortex_a715_regs: /* The ascii list of register names to be reported */ 75 .asciz "cpuectlr_el1", "" 76 77func cortex_a715_cpu_reg_dump 78 adr x6, cortex_a715_regs 79 mrs x8, CORTEX_A715_CPUECTLR_EL1 80 ret 81endfunc cortex_a715_cpu_reg_dump 82 83declare_cpu_ops cortex_a715, CORTEX_A715_MIDR, \ 84 cortex_a715_reset_func, \ 85 cortex_a715_core_pwr_dwn 86