1/* 2 * Copyright (c) 2021-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a715.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-A715 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-A715 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_A715_BHB_LOOP_COUNT, cortex_a715 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29workaround_reset_start cortex_a715, ERRATUM(2420947), ERRATA_A715_2420947 30 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(33) 31workaround_reset_end cortex_a715, ERRATUM(2420947) 32 33check_erratum_range cortex_a715, ERRATUM(2420947), CPU_REV(1, 0), CPU_REV(1, 0) 34 35workaround_reset_start cortex_a715, ERRATUM(2429384), ERRATA_A715_2429384 36 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(27) 37workaround_reset_end cortex_a715, ERRATUM(2429384) 38 39check_erratum_range cortex_a715, ERRATUM(2429384), CPU_REV(1, 0), CPU_REV(1, 0) 40 41workaround_runtime_start cortex_a715, ERRATUM(2561034), ERRATA_A715_2561034 42 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(26) 43workaround_runtime_end cortex_a715, ERRATUM(2561034), NO_ISB 44 45check_erratum_range cortex_a715, ERRATUM(2561034), CPU_REV(1, 0), CPU_REV(1, 0) 46 47workaround_reset_start cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 48#if IMAGE_BL31 49 /* 50 * The Cortex-A715 generic vectors are overridden to apply errata 51 * mitigation on exception entry from lower ELs. 52 */ 53 override_vector_table wa_cve_vbar_cortex_a715 54#endif /* IMAGE_BL31 */ 55workaround_reset_end cortex_a715, CVE(2022, 23960) 56 57check_erratum_chosen cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 58 59cpu_reset_func_start cortex_a715 60 /* Disable speculative loads */ 61 msr SSBS, xzr 62cpu_reset_func_end cortex_a715 63 64 /* ---------------------------------------------------- 65 * HW will do the cache maintenance while powering down 66 * ---------------------------------------------------- 67 */ 68func cortex_a715_core_pwr_dwn 69 /* --------------------------------------------------- 70 * Enable CPU power down bit in power control register 71 * --------------------------------------------------- 72 */ 73 mrs x0, CORTEX_A715_CPUPWRCTLR_EL1 74 orr x0, x0, #CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 75 msr CORTEX_A715_CPUPWRCTLR_EL1, x0 76 isb 77 ret 78endfunc cortex_a715_core_pwr_dwn 79 80errata_report_shim cortex_a715 81 82 /* --------------------------------------------- 83 * This function provides Cortex-A715 specific 84 * register information for crash reporting. 85 * It needs to return with x6 pointing to 86 * a list of register names in ascii and 87 * x8 - x15 having values of registers to be 88 * reported. 89 * --------------------------------------------- 90 */ 91.section .rodata.cortex_a715_regs, "aS" 92cortex_a715_regs: /* The ascii list of register names to be reported */ 93 .asciz "cpuectlr_el1", "" 94 95func cortex_a715_cpu_reg_dump 96 adr x6, cortex_a715_regs 97 mrs x8, CORTEX_A715_CPUECTLR_EL1 98 ret 99endfunc cortex_a715_cpu_reg_dump 100 101declare_cpu_ops cortex_a715, CORTEX_A715_MIDR, \ 102 cortex_a715_reset_func, \ 103 cortex_a715_core_pwr_dwn 104