1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a710.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14#include "wa_cve_2022_23960_bhb_vector.S" 15 16/* Hardware handled coherency */ 17#if HW_ASSISTED_COHERENCY == 0 18#error "Cortex A710 must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21/* 64-bit only core */ 22#if CTX_INCLUDE_AARCH32_REGS == 1 23#error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 24#endif 25 26.global check_erratum_cortex_a710_3701772 27 28#if WORKAROUND_CVE_2022_23960 29 wa_cve_2022_23960_bhb_vector_table CORTEX_A710_BHB_LOOP_COUNT, cortex_a710 30#endif /* WORKAROUND_CVE_2022_23960 */ 31 32cpu_reset_prologue cortex_a710 33 34workaround_reset_start cortex_a710, ERRATUM(1901946), ERRATA_A710_1901946 35 sysreg_bit_set CORTEX_A710_CPUACTLR4_EL1, BIT(15) 36workaround_reset_end cortex_a710, ERRATUM(1901946) 37 38check_erratum_range cortex_a710, ERRATUM(1901946), CPU_REV(1, 0), CPU_REV(1, 0) 39 40workaround_reset_start cortex_a710, ERRATUM(1916945), ERRATA_A710_1916945 41 sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, BIT(8) 42workaround_reset_end cortex_a710, ERRATUM(1916945) 43 44check_erratum_ls cortex_a710, ERRATUM(1916945), CPU_REV(1, 0) 45 46workaround_reset_start cortex_a710, ERRATUM(1917258), ERRATA_A710_1917258 47 sysreg_bit_set CORTEX_A710_CPUACTLR4_EL1, BIT(43) 48workaround_reset_end cortex_a710, ERRATUM(1917258) 49 50check_erratum_ls cortex_a710, ERRATUM(1917258), CPU_REV(1, 0) 51 52workaround_reset_start cortex_a710, ERRATUM(1987031), ERRATA_A710_1987031 53 ldr x0,=0x6 54 msr S3_6_c15_c8_0,x0 55 ldr x0,=0xF3A08002 56 msr S3_6_c15_c8_2,x0 57 ldr x0,=0xFFF0F7FE 58 msr S3_6_c15_c8_3,x0 59 ldr x0,=0x40000001003ff 60 msr S3_6_c15_c8_1,x0 61 ldr x0,=0x7 62 msr S3_6_c15_c8_0,x0 63 ldr x0,=0xBF200000 64 msr S3_6_c15_c8_2,x0 65 ldr x0,=0xFFEF0000 66 msr S3_6_c15_c8_3,x0 67 ldr x0,=0x40000001003f3 68 msr S3_6_c15_c8_1,x0 69workaround_reset_end cortex_a710, ERRATUM(1987031) 70 71check_erratum_ls cortex_a710, ERRATUM(1987031), CPU_REV(2, 0) 72 73workaround_runtime_start cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768 74 /* Stash ERRSELR_EL1 in x2 */ 75 mrs x2, ERRSELR_EL1 76 77 /* Select error record 0 and clear ED bit */ 78 msr ERRSELR_EL1, xzr 79 mrs x1, ERXCTLR_EL1 80 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 81 msr ERXCTLR_EL1, x1 82 83 /* Select error record 1 and clear ED bit */ 84 mov x0, #1 85 msr ERRSELR_EL1, x0 86 mrs x1, ERXCTLR_EL1 87 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 88 msr ERXCTLR_EL1, x1 89 90 /* Restore ERRSELR_EL1 from x2 */ 91 msr ERRSELR_EL1, x2 92workaround_runtime_end cortex_a710, ERRATUM(2008768), NO_ISB 93 94check_erratum_ls cortex_a710, ERRATUM(2008768), CPU_REV(2, 0) 95 96workaround_reset_start cortex_a710, ERRATUM(2017096), ERRATA_A710_2017096 97 sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT 98workaround_reset_end cortex_a710, ERRATUM(2017096) 99 100check_erratum_ls cortex_a710, ERRATUM(2017096), CPU_REV(2, 0) 101 102workaround_reset_start cortex_a710, ERRATUM(2055002), ERRATA_A710_2055002 103 sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_46 104workaround_reset_end cortex_a710, ERRATUM(2055002) 105 106check_erratum_range cortex_a710, ERRATUM(2055002), CPU_REV(1, 0), CPU_REV(2, 0) 107 108workaround_reset_start cortex_a710, ERRATUM(2081180), ERRATA_A710_2081180 109 ldr x0,=0x3 110 msr S3_6_c15_c8_0,x0 111 ldr x0,=0xF3A08002 112 msr S3_6_c15_c8_2,x0 113 ldr x0,=0xFFF0F7FE 114 msr S3_6_c15_c8_3,x0 115 ldr x0,=0x10002001003FF 116 msr S3_6_c15_c8_1,x0 117 ldr x0,=0x4 118 msr S3_6_c15_c8_0,x0 119 ldr x0,=0xBF200000 120 msr S3_6_c15_c8_2,x0 121 ldr x0,=0xFFEF0000 122 msr S3_6_c15_c8_3,x0 123 ldr x0,=0x10002001003F3 124 msr S3_6_c15_c8_1,x0 125workaround_reset_end cortex_a710, ERRATUM(2081180) 126 127check_erratum_ls cortex_a710, ERRATUM(2081180), CPU_REV(2, 0) 128 129workaround_reset_start cortex_a710, ERRATUM(2083908), ERRATA_A710_2083908 130 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_13 131workaround_reset_end cortex_a710, ERRATUM(2083908) 132 133check_erratum_range cortex_a710, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0) 134 135workaround_reset_start cortex_a710, ERRATUM(2136059), ERRATA_A710_2136059 136 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_44 137workaround_reset_end cortex_a710, ERRATUM(2136059) 138 139check_erratum_ls cortex_a710, ERRATUM(2136059), CPU_REV(2, 0) 140 141workaround_reset_start cortex_a710, ERRATUM(2147715), ERRATA_A710_2147715 142 sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22 143workaround_reset_end cortex_a710, ERRATUM(2147715) 144 145check_erratum_range cortex_a710, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0) 146 147workaround_reset_start cortex_a710, ERRATUM(2216384), ERRATA_A710_2216384 148 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_17 149 150 ldr x0,=0x5 151 msr CORTEX_A710_CPUPSELR_EL3, x0 152 ldr x0,=0x10F600E000 153 msr CORTEX_A710_CPUPOR_EL3, x0 154 ldr x0,=0x10FF80E000 155 msr CORTEX_A710_CPUPMR_EL3, x0 156 ldr x0,=0x80000000003FF 157 msr CORTEX_A710_CPUPCR_EL3, x0 158workaround_reset_end cortex_a710, ERRATUM(2216384) 159 160check_erratum_ls cortex_a710, ERRATUM(2216384), CPU_REV(2, 0) 161 162workaround_reset_start cortex_a710, ERRATUM(2267065), ERRATA_A710_2267065 163 sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22 164workaround_reset_end cortex_a710, ERRATUM(2267065) 165 166check_erratum_ls cortex_a710, ERRATUM(2267065), CPU_REV(2, 0) 167 168workaround_reset_start cortex_a710, ERRATUM(2282622), ERRATA_A710_2282622 169 sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, BIT(0) 170workaround_reset_end cortex_a710, ERRATUM(2282622) 171 172check_erratum_ls cortex_a710, ERRATUM(2282622), CPU_REV(2, 1) 173 174.global erratum_cortex_a710_2291219_wa 175workaround_runtime_start cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219 176 /* Set/unset bit 36 in ACTLR2_EL1. The first call will set it, applying 177 * the workaround. Second call clears it to undo it. */ 178 sysreg_bit_toggle CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_36 179workaround_runtime_end cortex_a710, ERRATUM(2291219), NO_ISB 180 181check_erratum_ls cortex_a710, ERRATUM(2291219), CPU_REV(2, 0) 182 183workaround_reset_start cortex_a710, ERRATUM(2313941), ERRATA_DSU_2313941 184 errata_dsu_2313941_wa_impl 185workaround_reset_end cortex_a710, ERRATUM(2313941) 186 187check_erratum_custom_start cortex_a710, ERRATUM(2313941) 188 check_errata_dsu_2313941_impl 189 ret 190check_erratum_custom_end cortex_a710, ERRATUM(2313941) 191 192workaround_reset_start cortex_a710, ERRATUM(2371105), ERRATA_A710_2371105 193 /* Set bit 40 in CPUACTLR2_EL1 */ 194 sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_40 195workaround_reset_end cortex_a710, ERRATUM(2371105) 196 197check_erratum_ls cortex_a710, ERRATUM(2371105), CPU_REV(2, 0) 198 199workaround_reset_start cortex_a710, ERRATUM(2742423), ERRATA_A710_2742423 200 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 201 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, BIT(55) 202 sysreg_bit_clear CORTEX_A710_CPUACTLR5_EL1, BIT(56) 203workaround_reset_end cortex_a710, ERRATUM(2742423) 204 205check_erratum_ls cortex_a710, ERRATUM(2742423), CPU_REV(2, 1) 206 207workaround_runtime_start cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515 208 /* dsb before isb of power down sequence */ 209 dsb sy 210workaround_runtime_end cortex_a710, ERRATUM(2768515), NO_ISB 211 212check_erratum_ls cortex_a710, ERRATUM(2768515), CPU_REV(2, 1) 213 214workaround_reset_start cortex_a710, ERRATUM(2778471), ERRATA_A710_2778471 215 sysreg_bit_set CORTEX_A710_CPUACTLR3_EL1, BIT(47) 216workaround_reset_end cortex_a710, ERRATUM(2778471) 217 218check_erratum_ls cortex_a710, ERRATUM(2778471), CPU_REV(2, 1) 219 220add_erratum_entry cortex_a710, ERRATUM(3701772), ERRATA_A710_3701772 221 222check_erratum_ls cortex_a710, ERRATUM(3701772), CPU_REV(2, 1) 223 224workaround_reset_start cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 225#if IMAGE_BL31 226 /* 227 * The Cortex-A710 generic vectors are overridden to apply errata 228 * mitigation on exception entry from lower ELs. 229 */ 230 override_vector_table wa_cve_vbar_cortex_a710 231#endif /* IMAGE_BL31 */ 232workaround_reset_end cortex_a710, CVE(2022, 23960) 233 234check_erratum_chosen cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 235 236/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 237workaround_reset_start cortex_a710, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 238 sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, BIT(46) 239workaround_reset_end cortex_a710, CVE(2024, 5660) 240 241check_erratum_ls cortex_a710, CVE(2024, 5660), CPU_REV(2, 1) 242 243 /* ---------------------------------------------------- 244 * HW will do the cache maintenance while powering down 245 * ---------------------------------------------------- 246 */ 247func cortex_a710_core_pwr_dwn 248 apply_erratum cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768, NO_GET_CPU_REV 249 apply_erratum cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219, NO_GET_CPU_REV 250 251 /* --------------------------------------------------- 252 * Enable CPU power down bit in power control register 253 * --------------------------------------------------- 254 */ 255 sysreg_bit_set CORTEX_A710_CPUPWRCTLR_EL1, CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 256 apply_erratum cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515, NO_GET_CPU_REV 257 isb 258 ret 259endfunc cortex_a710_core_pwr_dwn 260 261cpu_reset_func_start cortex_a710 262 /* Disable speculative loads */ 263 msr SSBS, xzr 264 enable_mpmm 265cpu_reset_func_end cortex_a710 266 267 /* --------------------------------------------- 268 * This function provides Cortex-A710 specific 269 * register information for crash reporting. 270 * It needs to return with x6 pointing to 271 * a list of register names in ascii and 272 * x8 - x15 having values of registers to be 273 * reported. 274 * --------------------------------------------- 275 */ 276.section .rodata.cortex_a710_regs, "aS" 277cortex_a710_regs: /* The ascii list of register names to be reported */ 278 .asciz "cpuectlr_el1", "" 279 280func cortex_a710_cpu_reg_dump 281 adr x6, cortex_a710_regs 282 mrs x8, CORTEX_A710_CPUECTLR_EL1 283 ret 284endfunc cortex_a710_cpu_reg_dump 285 286declare_cpu_ops cortex_a710, CORTEX_A710_MIDR, \ 287 cortex_a710_reset_func, \ 288 cortex_a710_core_pwr_dwn 289