1/* 2 * Copyright (c) 2021-2022, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a710.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex A710 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_A710_BHB_LOOP_COUNT, cortex_a710 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29/* -------------------------------------------------- 30 * Errata Workaround for Cortex-A710 Erratum 1987031. 31 * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710. It is still 32 * open. 33 * Inputs: 34 * x0: variant[4:7] and revision[0:3] of current cpu. 35 * Shall clobber: x0-x17 36 * -------------------------------------------------- 37 */ 38func errata_a710_1987031_wa 39 /* Check revision. */ 40 mov x17, x30 41 bl check_errata_1987031 42 cbz x0, 1f 43 44 /* Apply instruction patching sequence */ 45 ldr x0,=0x6 46 msr S3_6_c15_c8_0,x0 47 ldr x0,=0xF3A08002 48 msr S3_6_c15_c8_2,x0 49 ldr x0,=0xFFF0F7FE 50 msr S3_6_c15_c8_3,x0 51 ldr x0,=0x40000001003ff 52 msr S3_6_c15_c8_1,x0 53 ldr x0,=0x7 54 msr S3_6_c15_c8_0,x0 55 ldr x0,=0xBF200000 56 msr S3_6_c15_c8_2,x0 57 ldr x0,=0xFFEF0000 58 msr S3_6_c15_c8_3,x0 59 ldr x0,=0x40000001003f3 60 msr S3_6_c15_c8_1,x0 61 isb 621: 63 ret x17 64endfunc errata_a710_1987031_wa 65 66func check_errata_1987031 67 /* Applies to r0p0, r1p0 and r2p0 */ 68 mov x1, #0x20 69 b cpu_rev_var_ls 70endfunc check_errata_1987031 71 72/* -------------------------------------------------- 73 * Errata Workaround for Cortex-A710 Erratum 2081180. 74 * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710. 75 * It is still open. 76 * Inputs: 77 * x0: variant[4:7] and revision[0:3] of current cpu. 78 * Shall clobber: x0-x17 79 * -------------------------------------------------- 80 */ 81func errata_a710_2081180_wa 82 /* Check revision. */ 83 mov x17, x30 84 bl check_errata_2081180 85 cbz x0, 1f 86 87 /* Apply instruction patching sequence */ 88 ldr x0,=0x3 89 msr S3_6_c15_c8_0,x0 90 ldr x0,=0xF3A08002 91 msr S3_6_c15_c8_2,x0 92 ldr x0,=0xFFF0F7FE 93 msr S3_6_c15_c8_3,x0 94 ldr x0,=0x10002001003FF 95 msr S3_6_c15_c8_1,x0 96 ldr x0,=0x4 97 msr S3_6_c15_c8_0,x0 98 ldr x0,=0xBF200000 99 msr S3_6_c15_c8_2,x0 100 ldr x0,=0xFFEF0000 101 msr S3_6_c15_c8_3,x0 102 ldr x0,=0x10002001003F3 103 msr S3_6_c15_c8_1,x0 104 isb 1051: 106 ret x17 107endfunc errata_a710_2081180_wa 108 109func check_errata_2081180 110 /* Applies to r0p0, r1p0 and r2p0 */ 111 mov x1, #0x20 112 b cpu_rev_var_ls 113endfunc check_errata_2081180 114 115/* --------------------------------------------------------------------- 116 * Errata Workaround for Cortex-A710 Erratum 2055002. 117 * This applies to revision r1p0, r2p0 of Cortex-A710 and is still open. 118 * Inputs: 119 * x0: variant[4:7] and revision[0:3] of current cpu. 120 * Shall clobber: x0-x17 121 * --------------------------------------------------------------------- 122 */ 123func errata_a710_2055002_wa 124 /* Compare x0 against revision r2p0 */ 125 mov x17, x30 126 bl check_errata_2055002 127 cbz x0, 1f 128 mrs x1, CORTEX_A710_CPUACTLR_EL1 129 orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_46 130 msr CORTEX_A710_CPUACTLR_EL1, x1 1311: 132 ret x17 133endfunc errata_a710_2055002_wa 134 135func check_errata_2055002 136 /* Applies to r1p0, r2p0 */ 137 mov x1, #0x20 138 b cpu_rev_var_ls 139endfunc check_errata_2055002 140 141/* ------------------------------------------------------------- 142 * Errata Workaround for Cortex-A710 Erratum 2017096. 143 * This applies to revisions r0p0, r1p0 and r2p0 of Cortex-A710. 144 * Inputs: 145 * x0: variant[4:7] and revision[0:3] of current cpu. 146 * Shall clobber: x0-x17 147 * ------------------------------------------------------------- 148 */ 149func errata_a710_2017096_wa 150 /* Compare x0 against revision r0p0 to r2p0 */ 151 mov x17, x30 152 bl check_errata_2017096 153 cbz x0, 1f 154 mrs x1, CORTEX_A710_CPUECTLR_EL1 155 orr x1, x1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT 156 msr CORTEX_A710_CPUECTLR_EL1, x1 157 1581: 159 ret x17 160endfunc errata_a710_2017096_wa 161 162func check_errata_2017096 163 /* Applies to r0p0, r1p0, r2p0 */ 164 mov x1, #0x20 165 b cpu_rev_var_ls 166endfunc check_errata_2017096 167 168 169/* --------------------------------------------------------------------- 170 * Errata Workaround for Cortex-A710 Erratum 2083908. 171 * This applies to revision r2p0 of Cortex-A710 and is still open. 172 * Inputs: 173 * x0: variant[4:7] and revision[0:3] of current cpu. 174 * Shall clobber: x0-x17 175 * --------------------------------------------------------------------- 176 */ 177func errata_a710_2083908_wa 178 /* Compare x0 against revision r2p0 */ 179 mov x17, x30 180 bl check_errata_2083908 181 cbz x0, 1f 182 mrs x1, CORTEX_A710_CPUACTLR5_EL1 183 orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_13 184 msr CORTEX_A710_CPUACTLR5_EL1, x1 1851: 186 ret x17 187endfunc errata_a710_2083908_wa 188 189func check_errata_2083908 190 /* Applies to r2p0 */ 191 mov x1, #CPU_REV(2, 0) 192 mov x2, #CPU_REV(2, 0) 193 b cpu_rev_var_range 194endfunc check_errata_2083908 195 196/* --------------------------------------------------------------------- 197 * Errata Workaround for Cortex-A710 Erratum 2058056. 198 * This applies to revisions r0p0, r1p0 and r2p0 of Cortex-A710 and is still 199 * open. 200 * Inputs: 201 * x0: variant[4:7] and revision[0:3] of current cpu. 202 * Shall clobber: x0-x17 203 * --------------------------------------------------------------------- 204 */ 205func errata_a710_2058056_wa 206 /* Compare x0 against revision r2p0 */ 207 mov x17, x30 208 bl check_errata_2058056 209 cbz x0, 1f 210 mrs x1, CORTEX_A710_CPUECTLR2_EL1 211 mov x0, #CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV 212 bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH 213 msr CORTEX_A710_CPUECTLR2_EL1, x1 2141: 215 ret x17 216endfunc errata_a710_2058056_wa 217 218func check_errata_2058056 219 /* Applies to r0p0, r1p0 and r2p0 */ 220 mov x1, #0x20 221 b cpu_rev_var_ls 222endfunc check_errata_2058056 223 224/* -------------------------------------------------- 225 * Errata Workaround for Cortex-A710 Erratum 2267065. 226 * This applies to revisions r0p0, r1p0 and r2p0. 227 * It is fixed in r2p1. 228 * Inputs: 229 * x0: variant[4:7] and revision[0:3] of current cpu. 230 * Shall clobber: x0-x1, x17 231 * -------------------------------------------------- 232 */ 233func errata_a710_2267065_wa 234 /* Compare x0 against revision r2p0 */ 235 mov x17, x30 236 bl check_errata_2267065 237 cbz x0, 1f 238 239 /* Apply instruction patching sequence */ 240 mrs x1, CORTEX_A710_CPUACTLR_EL1 241 orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_22 242 msr CORTEX_A710_CPUACTLR_EL1, x1 2431: 244 ret x17 245endfunc errata_a710_2267065_wa 246 247func check_errata_2267065 248 /* Applies to r0p0, r1p0 and r2p0 */ 249 mov x1, #0x20 250 b cpu_rev_var_ls 251endfunc check_errata_2267065 252 253/* --------------------------------------------------------------- 254 * Errata Workaround for Cortex-A710 Erratum 2136059. 255 * This applies to revision r0p0, r1p0 and r2p0. 256 * It is fixed in r2p1. 257 * Inputs: 258 * x0: variant[4:7] and revision[0:3] of current cpu. 259 * Shall clobber: x0-x17 260 * --------------------------------------------------------------- 261 */ 262func errata_a710_2136059_wa 263 /* Compare x0 against revision r2p0 */ 264 mov x17, x30 265 bl check_errata_2136059 266 cbz x0, 1f 267 268 /* Apply the workaround */ 269 mrs x1, CORTEX_A710_CPUACTLR5_EL1 270 orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_44 271 msr CORTEX_A710_CPUACTLR5_EL1, x1 272 2731: 274 ret x17 275endfunc errata_a710_2136059_wa 276 277func check_errata_2136059 278 /* Applies to r0p0, r1p0 and r2p0 */ 279 mov x1, #0x20 280 b cpu_rev_var_ls 281endfunc check_errata_2136059 282 283/* ---------------------------------------------------------------- 284 * Errata workaround for Cortex-A710 Erratum 2147715. 285 * This applies to revision r2p0, and is fixed in r2p1. 286 * Inputs: 287 * x0: variant[4:7] and revision[0:3] of current cpu. 288 * Shall clobber: x0, x1, x17 289 * ---------------------------------------------------------------- 290 */ 291func errata_a710_2147715_wa 292 mov x17, x30 293 bl check_errata_2147715 294 cbz x0, 1f 295 296 /* Apply workaround; set CPUACTLR_EL1[22] 297 * to 1, which will cause the CFP instruction 298 * to invalidate all branch predictor resources 299 * regardless of context. 300 */ 301 mrs x1, CORTEX_A710_CPUACTLR_EL1 302 orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_22 303 msr CORTEX_A710_CPUACTLR_EL1, x1 3041: 305 ret x17 306endfunc errata_a710_2147715_wa 307 308func check_errata_2147715 309 mov x1, #0x20 310 mov x2, #0x20 311 b cpu_rev_var_range 312endfunc check_errata_2147715 313 314/* --------------------------------------------------------------- 315 * Errata Workaround for Cortex-A710 Erratum 2282622. 316 * This applies to revision r0p0, r1p0 and r2p0. 317 * It is fixed in r2p1. 318 * Inputs: 319 * x0: variant[4:7] and revision[0:3] of current cpu. 320 * Shall clobber: x0, x1, x17 321 * --------------------------------------------------------------- 322 */ 323func errata_a710_2282622_wa 324 /* Compare x0 against revision r2p0 */ 325 mov x17, x30 326 bl check_errata_2282622 327 cbz x0, 1f 328 329 /* Apply the workaround */ 330 mrs x1, CORTEX_A710_CPUACTLR2_EL1 331 orr x1, x1, BIT(0) 332 msr CORTEX_A710_CPUACTLR2_EL1, x1 333 3341: 335 ret x17 336endfunc errata_a710_2282622_wa 337 338func check_errata_2282622 339 /* Applies to r0p0, r1p0 and r2p0 */ 340 mov x1, #0x20 341 b cpu_rev_var_ls 342endfunc check_errata_2282622 343 344/* --------------------------------------------------------------- 345 * Errata Workaround for Cortex-A710 Erratum 2008768. 346 * This applies to revision r0p0, r1p0 and r2p0. 347 * It is fixed in r2p1. 348 * Inputs: 349 * x0: variant[4:7] and revision[0:3] of current cpu. 350 * Shall clobber: x0, x1, x2, x17 351 * --------------------------------------------------------------- 352 */ 353func errata_a710_2008768_wa 354 mov x17, x30 355 bl check_errata_2008768 356 cbz x0, 1f 357 358 /* Stash ERRSELR_EL1 in x2 */ 359 mrs x2, ERRSELR_EL1 360 361 /* Select error record 0 and clear ED bit */ 362 msr ERRSELR_EL1, xzr 363 mrs x1, ERXCTLR_EL1 364 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 365 msr ERXCTLR_EL1, x1 366 367 /* Select error record 1 and clear ED bit */ 368 mov x0, #1 369 msr ERRSELR_EL1, x0 370 mrs x1, ERXCTLR_EL1 371 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 372 msr ERXCTLR_EL1, x1 373 374 /* Restore ERRSELR_EL1 from x2 */ 375 msr ERRSELR_EL1, x2 376 3771: 378 ret x17 379endfunc errata_a710_2008768_wa 380 381func check_errata_2008768 382 /* Applies to r0p0, r1p0 and r2p0 */ 383 mov x1, #0x20 384 b cpu_rev_var_ls 385endfunc check_errata_2008768 386 387/* ------------------------------------------------------- 388 * Errata Workaround for Cortex-A710 Erratum 2371105. 389 * This applies to revisions <= r2p0 and is fixed in r2p1. 390 * x0: variant[4:7] and revision[0:3] of current cpu. 391 * Shall clobber: x0-x17 392 * ------------------------------------------------------- 393 */ 394func errata_a710_2371105_wa 395 /* Check workaround compatibility. */ 396 mov x17, x30 397 bl check_errata_2371105 398 cbz x0, 1f 399 400 /* Set bit 40 in CPUACTLR2_EL1 */ 401 mrs x1, CORTEX_A710_CPUACTLR2_EL1 402 orr x1, x1, #CORTEX_A710_CPUACTLR2_EL1_BIT_40 403 msr CORTEX_A710_CPUACTLR2_EL1, x1 404 isb 4051: 406 ret x17 407endfunc errata_a710_2371105_wa 408 409func check_errata_2371105 410 /* Applies to <= r2p0. */ 411 mov x1, #0x20 412 b cpu_rev_var_ls 413endfunc check_errata_2371105 414 415func check_errata_cve_2022_23960 416#if WORKAROUND_CVE_2022_23960 417 mov x0, #ERRATA_APPLIES 418#else 419 mov x0, #ERRATA_MISSING 420#endif 421 ret 422endfunc check_errata_cve_2022_23960 423 424 /* ---------------------------------------------------- 425 * HW will do the cache maintenance while powering down 426 * ---------------------------------------------------- 427 */ 428func cortex_a710_core_pwr_dwn 429 430#if ERRATA_A710_2008768 431 mov x4, x30 432 bl cpu_get_rev_var 433 bl errata_a710_2008768_wa 434 mov x30, x4 435#endif 436 437 /* --------------------------------------------------- 438 * Enable CPU power down bit in power control register 439 * --------------------------------------------------- 440 */ 441 mrs x0, CORTEX_A710_CPUPWRCTLR_EL1 442 orr x0, x0, #CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 443 msr CORTEX_A710_CPUPWRCTLR_EL1, x0 444 isb 445 ret 446endfunc cortex_a710_core_pwr_dwn 447 448#if REPORT_ERRATA 449 /* 450 * Errata printing function for Cortex-A710. Must follow AAPCS. 451 */ 452func cortex_a710_errata_report 453 stp x8, x30, [sp, #-16]! 454 455 bl cpu_get_rev_var 456 mov x8, x0 457 458 /* 459 * Report all errata. The revision-variant information is passed to 460 * checking functions of each errata. 461 */ 462 report_errata ERRATA_A710_1987031, cortex_a710, 1987031 463 report_errata ERRATA_A710_2081180, cortex_a710, 2081180 464 report_errata ERRATA_A710_2055002, cortex_a710, 2055002 465 report_errata ERRATA_A710_2017096, cortex_a710, 2017096 466 report_errata ERRATA_A710_2083908, cortex_a710, 2083908 467 report_errata ERRATA_A710_2058056, cortex_a710, 2058056 468 report_errata ERRATA_A710_2267065, cortex_a710, 2267065 469 report_errata ERRATA_A710_2136059, cortex_a710, 2136059 470 report_errata ERRATA_A710_2282622, cortex_a710, 2282622 471 report_errata ERRATA_A710_2008768, cortex_a710, 2008768 472 report_errata ERRATA_A710_2147715, cortex_a710, 2147715 473 report_errata ERRATA_A710_2371105, cortex_a710, 2371105 474 report_errata WORKAROUND_CVE_2022_23960, cortex_a710, cve_2022_23960 475 report_errata ERRATA_DSU_2313941, cortex_a710, dsu_2313941 476 477 ldp x8, x30, [sp], #16 478 ret 479endfunc cortex_a710_errata_report 480#endif 481 482func cortex_a710_reset_func 483 mov x19, x30 484 485 /* Disable speculative loads */ 486 msr SSBS, xzr 487 488 bl cpu_get_rev_var 489 mov x18, x0 490 491#if ERRATA_DSU_2313941 492 bl errata_dsu_2313941_wa 493#endif 494 495#if ERRATA_A710_1987031 496 mov x0, x18 497 bl errata_a710_1987031_wa 498#endif 499 500#if ERRATA_A710_2081180 501 mov x0, x18 502 bl errata_a710_2081180_wa 503#endif 504 505#if ERRATA_A710_2055002 506 mov x0, x18 507 bl errata_a710_2055002_wa 508#endif 509 510#if ERRATA_A710_2017096 511 mov x0, x18 512 bl errata_a710_2017096_wa 513#endif 514 515#if ERRATA_A710_2083908 516 mov x0, x18 517 bl errata_a710_2083908_wa 518#endif 519 520#if ERRATA_A710_2058056 521 mov x0, x18 522 bl errata_a710_2058056_wa 523#endif 524 525#if ERRATA_A710_2267065 526 mov x0, x18 527 bl errata_a710_2267065_wa 528#endif 529 530#if ERRATA_A710_2136059 531 mov x0, x18 532 bl errata_a710_2136059_wa 533#endif 534 535#if ERRATA_A710_2147715 536 mov x0, x18 537 bl errata_a710_2147715_wa 538#endif 539 540#if ERRATA_A710_2282622 541 mov x0, x18 542 bl errata_a710_2282622_wa 543#endif 544 545#if ERRATA_A710_2371105 546 mov x0, x18 547 bl errata_a710_2371105_wa 548#endif 549 550#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 551 /* 552 * The Cortex-A710 generic vectors are overridden to apply errata 553 * mitigation on exception entry from lower ELs. 554 */ 555 adr x0, wa_cve_vbar_cortex_a710 556 msr vbar_el3, x0 557#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ 558 559 isb 560 ret x19 561endfunc cortex_a710_reset_func 562 563 /* --------------------------------------------- 564 * This function provides Cortex-A710 specific 565 * register information for crash reporting. 566 * It needs to return with x6 pointing to 567 * a list of register names in ascii and 568 * x8 - x15 having values of registers to be 569 * reported. 570 * --------------------------------------------- 571 */ 572.section .rodata.cortex_a710_regs, "aS" 573cortex_a710_regs: /* The ascii list of register names to be reported */ 574 .asciz "cpuectlr_el1", "" 575 576func cortex_a710_cpu_reg_dump 577 adr x6, cortex_a710_regs 578 mrs x8, CORTEX_A710_CPUECTLR_EL1 579 ret 580endfunc cortex_a710_cpu_reg_dump 581 582declare_cpu_ops cortex_a710, CORTEX_A710_MIDR, \ 583 cortex_a710_reset_func, \ 584 cortex_a710_core_pwr_dwn 585