1/* 2 * Copyright (c) 2021-2022, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a710.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex A710 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_A710_BHB_LOOP_COUNT, cortex_a710 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29/* -------------------------------------------------- 30 * Errata Workaround for Cortex-A710 Erratum 1987031. 31 * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710. It is still 32 * open. 33 * Inputs: 34 * x0: variant[4:7] and revision[0:3] of current cpu. 35 * Shall clobber: x0-x17 36 * -------------------------------------------------- 37 */ 38func errata_a710_1987031_wa 39 /* Check revision. */ 40 mov x17, x30 41 bl check_errata_1987031 42 cbz x0, 1f 43 44 /* Apply instruction patching sequence */ 45 ldr x0,=0x6 46 msr S3_6_c15_c8_0,x0 47 ldr x0,=0xF3A08002 48 msr S3_6_c15_c8_2,x0 49 ldr x0,=0xFFF0F7FE 50 msr S3_6_c15_c8_3,x0 51 ldr x0,=0x40000001003ff 52 msr S3_6_c15_c8_1,x0 53 ldr x0,=0x7 54 msr S3_6_c15_c8_0,x0 55 ldr x0,=0xBF200000 56 msr S3_6_c15_c8_2,x0 57 ldr x0,=0xFFEF0000 58 msr S3_6_c15_c8_3,x0 59 ldr x0,=0x40000001003f3 60 msr S3_6_c15_c8_1,x0 61 isb 621: 63 ret x17 64endfunc errata_a710_1987031_wa 65 66func check_errata_1987031 67 /* Applies to r0p0, r1p0 and r2p0 */ 68 mov x1, #0x20 69 b cpu_rev_var_ls 70endfunc check_errata_1987031 71 72/* -------------------------------------------------- 73 * Errata Workaround for Cortex-A710 Erratum 2081180. 74 * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710. 75 * It is still open. 76 * Inputs: 77 * x0: variant[4:7] and revision[0:3] of current cpu. 78 * Shall clobber: x0-x17 79 * -------------------------------------------------- 80 */ 81func errata_a710_2081180_wa 82 /* Check revision. */ 83 mov x17, x30 84 bl check_errata_2081180 85 cbz x0, 1f 86 87 /* Apply instruction patching sequence */ 88 ldr x0,=0x3 89 msr S3_6_c15_c8_0,x0 90 ldr x0,=0xF3A08002 91 msr S3_6_c15_c8_2,x0 92 ldr x0,=0xFFF0F7FE 93 msr S3_6_c15_c8_3,x0 94 ldr x0,=0x10002001003FF 95 msr S3_6_c15_c8_1,x0 96 ldr x0,=0x4 97 msr S3_6_c15_c8_0,x0 98 ldr x0,=0xBF200000 99 msr S3_6_c15_c8_2,x0 100 ldr x0,=0xFFEF0000 101 msr S3_6_c15_c8_3,x0 102 ldr x0,=0x10002001003F3 103 msr S3_6_c15_c8_1,x0 104 isb 1051: 106 ret x17 107endfunc errata_a710_2081180_wa 108 109func check_errata_2081180 110 /* Applies to r0p0, r1p0 and r2p0 */ 111 mov x1, #0x20 112 b cpu_rev_var_ls 113endfunc check_errata_2081180 114 115/* --------------------------------------------------------------------- 116 * Errata Workaround for Cortex-A710 Erratum 2055002. 117 * This applies to revision r1p0, r2p0 of Cortex-A710 and is still open. 118 * Inputs: 119 * x0: variant[4:7] and revision[0:3] of current cpu. 120 * Shall clobber: x0-x17 121 * --------------------------------------------------------------------- 122 */ 123func errata_a710_2055002_wa 124 /* Compare x0 against revision r2p0 */ 125 mov x17, x30 126 bl check_errata_2055002 127 cbz x0, 1f 128 mrs x1, CORTEX_A710_CPUACTLR_EL1 129 orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_46 130 msr CORTEX_A710_CPUACTLR_EL1, x1 1311: 132 ret x17 133endfunc errata_a710_2055002_wa 134 135func check_errata_2055002 136 /* Applies to r1p0, r2p0 */ 137 mov x1, #0x20 138 b cpu_rev_var_ls 139endfunc check_errata_2055002 140 141/* ------------------------------------------------------------- 142 * Errata Workaround for Cortex-A710 Erratum 2017096. 143 * This applies to revisions r0p0, r1p0 and r2p0 of Cortex-A710. 144 * Inputs: 145 * x0: variant[4:7] and revision[0:3] of current cpu. 146 * Shall clobber: x0-x17 147 * ------------------------------------------------------------- 148 */ 149func errata_a710_2017096_wa 150 /* Compare x0 against revision r0p0 to r2p0 */ 151 mov x17, x30 152 bl check_errata_2017096 153 cbz x0, 1f 154 mrs x1, CORTEX_A710_CPUECTLR_EL1 155 orr x1, x1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT 156 msr CORTEX_A710_CPUECTLR_EL1, x1 157 1581: 159 ret x17 160endfunc errata_a710_2017096_wa 161 162func check_errata_2017096 163 /* Applies to r0p0, r1p0, r2p0 */ 164 mov x1, #0x20 165 b cpu_rev_var_ls 166endfunc check_errata_2017096 167 168 169/* --------------------------------------------------------------------- 170 * Errata Workaround for Cortex-A710 Erratum 2083908. 171 * This applies to revision r2p0 of Cortex-A710 and is still open. 172 * Inputs: 173 * x0: variant[4:7] and revision[0:3] of current cpu. 174 * Shall clobber: x0-x17 175 * --------------------------------------------------------------------- 176 */ 177func errata_a710_2083908_wa 178 /* Compare x0 against revision r2p0 */ 179 mov x17, x30 180 bl check_errata_2083908 181 cbz x0, 1f 182 mrs x1, CORTEX_A710_CPUACTLR5_EL1 183 orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_13 184 msr CORTEX_A710_CPUACTLR5_EL1, x1 1851: 186 ret x17 187endfunc errata_a710_2083908_wa 188 189func check_errata_2083908 190 /* Applies to r2p0 */ 191 mov x1, #CPU_REV(2, 0) 192 mov x2, #CPU_REV(2, 0) 193 b cpu_rev_var_range 194endfunc check_errata_2083908 195 196/* --------------------------------------------------------------------- 197 * Errata Workaround for Cortex-A710 Erratum 2058056. 198 * This applies to revisions r0p0, r1p0 and r2p0 of Cortex-A710 and is still 199 * open. 200 * Inputs: 201 * x0: variant[4:7] and revision[0:3] of current cpu. 202 * Shall clobber: x0-x17 203 * --------------------------------------------------------------------- 204 */ 205func errata_a710_2058056_wa 206 /* Compare x0 against revision r2p0 */ 207 mov x17, x30 208 bl check_errata_2058056 209 cbz x0, 1f 210 mrs x1, CORTEX_A710_CPUECTLR2_EL1 211 mov x0, #CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV 212 bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH 213 msr CORTEX_A710_CPUECTLR2_EL1, x1 2141: 215 ret x17 216endfunc errata_a710_2058056_wa 217 218func check_errata_2058056 219 /* Applies to r0p0, r1p0 and r2p0 */ 220 mov x1, #0x20 221 b cpu_rev_var_ls 222endfunc check_errata_2058056 223 224/* -------------------------------------------------- 225 * Errata Workaround for Cortex-A710 Erratum 2267065. 226 * This applies to revisions r0p0, r1p0 and r2p0. 227 * It is fixed in r2p1. 228 * Inputs: 229 * x0: variant[4:7] and revision[0:3] of current cpu. 230 * Shall clobber: x0-x1, x17 231 * -------------------------------------------------- 232 */ 233func errata_a710_2267065_wa 234 /* Compare x0 against revision r2p0 */ 235 mov x17, x30 236 bl check_errata_2267065 237 cbz x0, 1f 238 239 /* Apply instruction patching sequence */ 240 mrs x1, CORTEX_A710_CPUACTLR_EL1 241 orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_22 242 msr CORTEX_A710_CPUACTLR_EL1, x1 2431: 244 ret x17 245endfunc errata_a710_2267065_wa 246 247func check_errata_2267065 248 /* Applies to r0p0, r1p0 and r2p0 */ 249 mov x1, #0x20 250 b cpu_rev_var_ls 251endfunc check_errata_2267065 252 253/* --------------------------------------------------------------- 254 * Errata Workaround for Cortex-A710 Erratum 2136059. 255 * This applies to revision r0p0, r1p0 and r2p0. 256 * It is fixed in r2p1. 257 * Inputs: 258 * x0: variant[4:7] and revision[0:3] of current cpu. 259 * Shall clobber: x0-x17 260 * --------------------------------------------------------------- 261 */ 262func errata_a710_2136059_wa 263 /* Compare x0 against revision r2p0 */ 264 mov x17, x30 265 bl check_errata_2136059 266 cbz x0, 1f 267 268 /* Apply the workaround */ 269 mrs x1, CORTEX_A710_CPUACTLR5_EL1 270 orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_44 271 msr CORTEX_A710_CPUACTLR5_EL1, x1 272 2731: 274 ret x17 275endfunc errata_a710_2136059_wa 276 277func check_errata_2136059 278 /* Applies to r0p0, r1p0 and r2p0 */ 279 mov x1, #0x20 280 b cpu_rev_var_ls 281endfunc check_errata_2136059 282 283/* --------------------------------------------------------------- 284 * Errata Workaround for Cortex-A710 Erratum 2282622. 285 * This applies to revision r0p0, r1p0 and r2p0. 286 * It is fixed in r2p1. 287 * Inputs: 288 * x0: variant[4:7] and revision[0:3] of current cpu. 289 * Shall clobber: x0, x1, x17 290 * --------------------------------------------------------------- 291 */ 292func errata_a710_2282622_wa 293 /* Compare x0 against revision r2p0 */ 294 mov x17, x30 295 bl check_errata_2282622 296 cbz x0, 1f 297 298 /* Apply the workaround */ 299 mrs x1, CORTEX_A710_CPUACTLR2_EL1 300 orr x1, x1, BIT(0) 301 msr CORTEX_A710_CPUACTLR2_EL1, x1 302 3031: 304 ret x17 305endfunc errata_a710_2282622_wa 306 307func check_errata_2282622 308 /* Applies to r0p0, r1p0 and r2p0 */ 309 mov x1, #0x20 310 b cpu_rev_var_ls 311endfunc check_errata_2282622 312 313func check_errata_cve_2022_23960 314#if WORKAROUND_CVE_2022_23960 315 mov x0, #ERRATA_APPLIES 316#else 317 mov x0, #ERRATA_MISSING 318#endif 319 ret 320endfunc check_errata_cve_2022_23960 321 322 /* ---------------------------------------------------- 323 * HW will do the cache maintenance while powering down 324 * ---------------------------------------------------- 325 */ 326func cortex_a710_core_pwr_dwn 327 /* --------------------------------------------------- 328 * Enable CPU power down bit in power control register 329 * --------------------------------------------------- 330 */ 331 mrs x0, CORTEX_A710_CPUPWRCTLR_EL1 332 orr x0, x0, #CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 333 msr CORTEX_A710_CPUPWRCTLR_EL1, x0 334 isb 335 ret 336endfunc cortex_a710_core_pwr_dwn 337 338#if REPORT_ERRATA 339 /* 340 * Errata printing function for Cortex-A710. Must follow AAPCS. 341 */ 342func cortex_a710_errata_report 343 stp x8, x30, [sp, #-16]! 344 345 bl cpu_get_rev_var 346 mov x8, x0 347 348 /* 349 * Report all errata. The revision-variant information is passed to 350 * checking functions of each errata. 351 */ 352 report_errata ERRATA_A710_1987031, cortex_a710, 1987031 353 report_errata ERRATA_A710_2081180, cortex_a710, 2081180 354 report_errata ERRATA_A710_2055002, cortex_a710, 2055002 355 report_errata ERRATA_A710_2017096, cortex_a710, 2017096 356 report_errata ERRATA_A710_2083908, cortex_a710, 2083908 357 report_errata ERRATA_A710_2058056, cortex_a710, 2058056 358 report_errata ERRATA_A710_2267065, cortex_a710, 2267065 359 report_errata ERRATA_A710_2136059, cortex_a710, 2136059 360 report_errata ERRATA_A710_2282622, cortex_a710, 2282622 361 report_errata WORKAROUND_CVE_2022_23960, cortex_a710, cve_2022_23960 362 363 ldp x8, x30, [sp], #16 364 ret 365endfunc cortex_a710_errata_report 366#endif 367 368func cortex_a710_reset_func 369 mov x19, x30 370 371 /* Disable speculative loads */ 372 msr SSBS, xzr 373 374 bl cpu_get_rev_var 375 mov x18, x0 376 377#if ERRATA_A710_1987031 378 mov x0, x18 379 bl errata_a710_1987031_wa 380#endif 381 382#if ERRATA_A710_2081180 383 mov x0, x18 384 bl errata_a710_2081180_wa 385#endif 386 387#if ERRATA_A710_2055002 388 mov x0, x18 389 bl errata_a710_2055002_wa 390#endif 391 392#if ERRATA_A710_2017096 393 mov x0, x18 394 bl errata_a710_2017096_wa 395#endif 396 397#if ERRATA_A710_2083908 398 mov x0, x18 399 bl errata_a710_2083908_wa 400#endif 401 402#if ERRATA_A710_2058056 403 mov x0, x18 404 bl errata_a710_2058056_wa 405#endif 406 407#if ERRATA_A710_2267065 408 mov x0, x18 409 bl errata_a710_2267065_wa 410#endif 411 412#if ERRATA_A710_2136059 413 mov x0, x18 414 bl errata_a710_2136059_wa 415#endif 416 417#if ERRATA_A710_2282622 418 mov x0, x18 419 bl errata_a710_2282622_wa 420#endif 421 422#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 423 /* 424 * The Cortex-A710 generic vectors are overridden to apply errata 425 * mitigation on exception entry from lower ELs. 426 */ 427 adr x0, wa_cve_vbar_cortex_a710 428 msr vbar_el3, x0 429#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ 430 431 isb 432 ret x19 433endfunc cortex_a710_reset_func 434 435 /* --------------------------------------------- 436 * This function provides Cortex-A710 specific 437 * register information for crash reporting. 438 * It needs to return with x6 pointing to 439 * a list of register names in ascii and 440 * x8 - x15 having values of registers to be 441 * reported. 442 * --------------------------------------------- 443 */ 444.section .rodata.cortex_a710_regs, "aS" 445cortex_a710_regs: /* The ascii list of register names to be reported */ 446 .asciz "cpuectlr_el1", "" 447 448func cortex_a710_cpu_reg_dump 449 adr x6, cortex_a710_regs 450 mrs x8, CORTEX_A710_CPUECTLR_EL1 451 ret 452endfunc cortex_a710_cpu_reg_dump 453 454declare_cpu_ops cortex_a710, CORTEX_A710_MIDR, \ 455 cortex_a710_reset_func, \ 456 cortex_a710_core_pwr_dwn 457