1/* 2 * Copyright (c) 2021-2026, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a710.h> 11#include <cpu_macros.S> 12#include "wa_cve_2022_23960_bhb_vector.S" 13 14#include <dsu_macros.S> 15#include <wa_cve_2025_0647_cpprctx.h> 16 17#include <plat_macros.S> 18 19/* Hardware handled coherency */ 20#if HW_ASSISTED_COHERENCY == 0 21#error "Cortex A710 must be compiled with HW_ASSISTED_COHERENCY enabled" 22#endif 23 24/* 64-bit only core */ 25#if CTX_INCLUDE_AARCH32_REGS == 1 26#error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 27#endif 28 29.global check_erratum_cortex_a710_3701772 30 31#if WORKAROUND_CVE_2022_23960 32 wa_cve_2022_23960_bhb_vector_table CORTEX_A710_BHB_LOOP_COUNT, cortex_a710 33#endif /* WORKAROUND_CVE_2022_23960 */ 34 35cpu_reset_prologue cortex_a710 36 37workaround_reset_start cortex_a710, ERRATUM(1785648), ERRATA_A710_1785648 38 sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, BIT(2) 39workaround_reset_end cortex_a710, ERRATUM(1785648) 40 41check_erratum_ls cortex_a710, ERRATUM(1785648), CPU_REV(0, 0) 42 43workaround_reset_start cortex_a710, ERRATUM(1793423), ERRATA_A710_1793423 44 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, BIT(10) 45workaround_reset_end cortex_a710, ERRATUM(1793423) 46 47check_erratum_ls cortex_a710, ERRATUM(1793423), CPU_REV(0, 0) 48 49workaround_reset_start cortex_a710, ERRATUM(1847092), ERRATA_A710_1847092 50 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, BIT(10) 51workaround_reset_end cortex_a710, ERRATUM(1847092) 52 53check_erratum_ls cortex_a710, ERRATUM(1847092), CPU_REV(0, 0) 54 55workaround_reset_start cortex_a710, ERRATUM(1887102), ERRATA_A710_1887102 56 sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, BIT(27) 57workaround_reset_end cortex_a710, ERRATUM(1887102) 58 59check_erratum_ls cortex_a710, ERRATUM(1887102), CPU_REV(1, 0) 60 61workaround_reset_start cortex_a710, ERRATUM(1901946), ERRATA_A710_1901946 62 sysreg_bit_set CORTEX_A710_CPUACTLR4_EL1, BIT(15) 63workaround_reset_end cortex_a710, ERRATUM(1901946) 64 65check_erratum_range cortex_a710, ERRATUM(1901946), CPU_REV(1, 0), CPU_REV(1, 0) 66 67workaround_reset_start cortex_a710, ERRATUM(1916945), ERRATA_A710_1916945 68 sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, BIT(8) 69workaround_reset_end cortex_a710, ERRATUM(1916945) 70 71check_erratum_ls cortex_a710, ERRATUM(1916945), CPU_REV(1, 0) 72 73workaround_reset_start cortex_a710, ERRATUM(1917258), ERRATA_A710_1917258 74 sysreg_bit_set CORTEX_A710_CPUACTLR4_EL1, BIT(43) 75workaround_reset_end cortex_a710, ERRATUM(1917258) 76 77check_erratum_ls cortex_a710, ERRATUM(1917258), CPU_REV(1, 0) 78 79workaround_reset_start cortex_a710, ERRATUM(1927200), ERRATA_A710_1927200 80 mov x0, #0 81 msr S3_6_C15_C8_0, x0 82 ldr x0, =0x10E3900002 83 msr S3_6_C15_C8_2, x0 84 ldr x0, =0x10FFF00083 85 msr S3_6_C15_C8_3, x0 86 ldr x0, =0x2001003FF 87 msr S3_6_C15_C8_1, x0 88 89 mov x0, #1 90 msr S3_6_C15_C8_0, x0 91 ldr x0, =0x10E3800082 92 msr S3_6_C15_C8_2, x0 93 ldr x0, =0x10FFF00083 94 msr S3_6_C15_C8_3, x0 95 ldr x0, =0x2001003FF 96 msr S3_6_C15_C8_1, x0 97 98 mov x0, #2 99 msr S3_6_C15_C8_0, x0 100 ldr x0, =0x10E3800200 101 msr S3_6_C15_C8_2, x0 102 ldr x0, =0x10FFF003E0 103 msr S3_6_C15_C8_3, x0 104 ldr x0, =0x2001003FF 105 msr S3_6_C15_C8_1, x0 106workaround_reset_end cortex_a710, ERRATUM(1927200) 107 108check_erratum_ls cortex_a710, ERRATUM(1927200), CPU_REV(1, 0) 109 110workaround_reset_start cortex_a710, ERRATUM(1987031), ERRATA_A710_1987031 111 ldr x0,=0x6 112 msr S3_6_c15_c8_0,x0 113 ldr x0,=0xF3A08002 114 msr S3_6_c15_c8_2,x0 115 ldr x0,=0xFFF0F7FE 116 msr S3_6_c15_c8_3,x0 117 ldr x0,=0x40000001003ff 118 msr S3_6_c15_c8_1,x0 119 ldr x0,=0x7 120 msr S3_6_c15_c8_0,x0 121 ldr x0,=0xBF200000 122 msr S3_6_c15_c8_2,x0 123 ldr x0,=0xFFEF0000 124 msr S3_6_c15_c8_3,x0 125 ldr x0,=0x40000001003f3 126 msr S3_6_c15_c8_1,x0 127workaround_reset_end cortex_a710, ERRATUM(1987031) 128 129check_erratum_ls cortex_a710, ERRATUM(1987031), CPU_REV(2, 0) 130 131workaround_runtime_start cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768 132 /* Stash ERRSELR_EL1 in x2 */ 133 mrs x2, ERRSELR_EL1 134 135 /* Select error record 0 and clear ED bit */ 136 msr ERRSELR_EL1, xzr 137 mrs x1, ERXCTLR_EL1 138 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 139 msr ERXCTLR_EL1, x1 140 141 /* Select error record 1 and clear ED bit */ 142 mov x0, #1 143 msr ERRSELR_EL1, x0 144 mrs x1, ERXCTLR_EL1 145 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 146 msr ERXCTLR_EL1, x1 147 148 /* Restore ERRSELR_EL1 from x2 */ 149 msr ERRSELR_EL1, x2 150workaround_runtime_end cortex_a710, ERRATUM(2008768), NO_ISB 151 152check_erratum_ls cortex_a710, ERRATUM(2008768), CPU_REV(2, 0) 153 154workaround_reset_start cortex_a710, ERRATUM(2017096), ERRATA_A710_2017096 155 sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT 156workaround_reset_end cortex_a710, ERRATUM(2017096) 157 158check_erratum_ls cortex_a710, ERRATUM(2017096), CPU_REV(2, 0) 159 160workaround_reset_start cortex_a710, ERRATUM(2055002), ERRATA_A710_2055002 161 sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_46 162workaround_reset_end cortex_a710, ERRATUM(2055002) 163 164check_erratum_range cortex_a710, ERRATUM(2055002), CPU_REV(1, 0), CPU_REV(2, 0) 165 166workaround_reset_start cortex_a710, ERRATUM(2081180), ERRATA_A710_2081180 167 ldr x0,=0x3 168 msr S3_6_c15_c8_0,x0 169 ldr x0,=0xF3A08002 170 msr S3_6_c15_c8_2,x0 171 ldr x0,=0xFFF0F7FE 172 msr S3_6_c15_c8_3,x0 173 ldr x0,=0x10002001003FF 174 msr S3_6_c15_c8_1,x0 175 ldr x0,=0x4 176 msr S3_6_c15_c8_0,x0 177 ldr x0,=0xBF200000 178 msr S3_6_c15_c8_2,x0 179 ldr x0,=0xFFEF0000 180 msr S3_6_c15_c8_3,x0 181 ldr x0,=0x10002001003F3 182 msr S3_6_c15_c8_1,x0 183workaround_reset_end cortex_a710, ERRATUM(2081180) 184 185check_erratum_ls cortex_a710, ERRATUM(2081180), CPU_REV(2, 0) 186 187workaround_reset_start cortex_a710, ERRATUM(2083908), ERRATA_A710_2083908 188 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_13 189workaround_reset_end cortex_a710, ERRATUM(2083908) 190 191check_erratum_range cortex_a710, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0) 192 193workaround_reset_start cortex_a710, ERRATUM(2136059), ERRATA_A710_2136059 194 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_44 195workaround_reset_end cortex_a710, ERRATUM(2136059) 196 197check_erratum_ls cortex_a710, ERRATUM(2136059), CPU_REV(2, 0) 198 199workaround_reset_start cortex_a710, ERRATUM(2147715), ERRATA_A710_2147715 200 sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22 201workaround_reset_end cortex_a710, ERRATUM(2147715) 202 203check_erratum_range cortex_a710, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0) 204 205workaround_reset_start cortex_a710, ERRATUM(2216384), ERRATA_A710_2216384 206 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_17 207 208 ldr x0,=0x5 209 msr CORTEX_A710_CPUPSELR_EL3, x0 210 ldr x0,=0x10F600E000 211 msr CORTEX_A710_CPUPOR_EL3, x0 212 ldr x0,=0x10FF80E000 213 msr CORTEX_A710_CPUPMR_EL3, x0 214 ldr x0,=0x80000000003FF 215 msr CORTEX_A710_CPUPCR_EL3, x0 216workaround_reset_end cortex_a710, ERRATUM(2216384) 217 218check_erratum_ls cortex_a710, ERRATUM(2216384), CPU_REV(2, 0) 219 220workaround_reset_start cortex_a710, ERRATUM(2267065), ERRATA_A710_2267065 221 sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22 222workaround_reset_end cortex_a710, ERRATUM(2267065) 223 224check_erratum_ls cortex_a710, ERRATUM(2267065), CPU_REV(2, 0) 225 226workaround_reset_start cortex_a710, ERRATUM(2282622), ERRATA_A710_2282622 227 sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, BIT(0) 228workaround_reset_end cortex_a710, ERRATUM(2282622) 229 230check_erratum_ls cortex_a710, ERRATUM(2282622), CPU_REV(2, 1) 231 232.global erratum_cortex_a710_2291219_wa 233workaround_runtime_start cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219 234 /* Set/unset bit 36 in ACTLR2_EL1. The first call will set it, applying 235 * the workaround. Second call clears it to undo it. */ 236 sysreg_bit_toggle CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_36 237workaround_runtime_end cortex_a710, ERRATUM(2291219), NO_ISB 238 239check_erratum_ls cortex_a710, ERRATUM(2291219), CPU_REV(2, 0) 240 241workaround_reset_start cortex_a710, ERRATUM(2313941), ERRATA_DSU_2313941 242 errata_dsu_2313941_wa_impl 243workaround_reset_end cortex_a710, ERRATUM(2313941) 244 245check_erratum_custom_start cortex_a710, ERRATUM(2313941) 246 check_errata_dsu_2313941_impl 247 ret 248check_erratum_custom_end cortex_a710, ERRATUM(2313941) 249 250workaround_reset_start cortex_a710, ERRATUM(2371105), ERRATA_A710_2371105 251 /* Set bit 40 in CPUACTLR2_EL1 */ 252 sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_40 253workaround_reset_end cortex_a710, ERRATUM(2371105) 254 255check_erratum_ls cortex_a710, ERRATUM(2371105), CPU_REV(2, 0) 256 257workaround_reset_start cortex_a710, ERRATUM(2742423), ERRATA_A710_2742423 258 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 259 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, BIT(55) 260 sysreg_bit_clear CORTEX_A710_CPUACTLR5_EL1, BIT(56) 261workaround_reset_end cortex_a710, ERRATUM(2742423) 262 263check_erratum_ls cortex_a710, ERRATUM(2742423), CPU_REV(2, 1) 264 265workaround_runtime_start cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515 266 /* dsb before isb of power down sequence */ 267 dsb sy 268workaround_runtime_end cortex_a710, ERRATUM(2768515), NO_ISB 269 270check_erratum_ls cortex_a710, ERRATUM(2768515), CPU_REV(2, 1) 271 272workaround_reset_start cortex_a710, ERRATUM(2778471), ERRATA_A710_2778471 273 sysreg_bit_set CORTEX_A710_CPUACTLR3_EL1, BIT(47) 274workaround_reset_end cortex_a710, ERRATUM(2778471) 275 276check_erratum_ls cortex_a710, ERRATUM(2778471), CPU_REV(2, 1) 277 278workaround_runtime_start cortex_a710, ERRATUM(3324338), ERRATA_A710_3324338 279 speculation_barrier 280workaround_runtime_end cortex_a710, ERRATUM(3324338) 281 282check_erratum_ls cortex_a710, ERRATUM(3324338), CPU_REV(2, 1) 283 284workaround_reset_start cortex_a710, ERRATUM(3888122), ERRATA_A710_3888122 285 sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, BIT(22) 286workaround_reset_end cortex_a710, ERRATUM(3888122) 287 288check_erratum_chosen cortex_a710, ERRATUM(3888122), ERRATA_A710_3888122 289 290workaround_reset_start cortex_a710, ERRATUM(4302969), ERRATA_A710_4302969 291 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, BIT(50) 292workaround_reset_end cortex_a710, ERRATUM(4302969) 293 294check_erratum_chosen cortex_a710, ERRATUM(4302969), ERRATA_A710_4302969 295 296add_erratum_entry cortex_a710, ERRATUM(3701772), ERRATA_A710_3701772 297 298check_erratum_ls cortex_a710, ERRATUM(3701772), CPU_REV(2, 1) 299 300workaround_reset_start cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 301#if IMAGE_BL31 302 /* 303 * The Cortex-A710 generic vectors are overridden to apply errata 304 * mitigation on exception entry from lower ELs. 305 */ 306 override_vector_table wa_cve_vbar_cortex_a710 307#endif /* IMAGE_BL31 */ 308workaround_reset_end cortex_a710, CVE(2022, 23960) 309 310check_erratum_chosen cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 311 312/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 313workaround_reset_start cortex_a710, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 314 sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, BIT(46) 315workaround_reset_end cortex_a710, CVE(2024, 5660) 316 317check_erratum_ls cortex_a710, CVE(2024, 5660), CPU_REV(2, 1) 318 319 /* 320 * Instruction patch sequence to trap 'cpp rctx' instructions to EL3. 321 * Enables mitigation for CVE-2025-0647. 322 */ 323workaround_reset_start cortex_a710, CVE(2025, 647), WORKAROUND_CVE_2025_0647 324#if IMAGE_BL31 325 mov x0, #(WA_USE_T32_OPCODE | WA_PATCH_SLOT(0)) 326 bl wa_cve_2025_0647_instruction_patch 327#endif /* IMAGE_BL31 */ 328workaround_reset_end cortex_a710, CVE(2025, 647) 329 330check_erratum_chosen cortex_a710, CVE(2025, 647), WORKAROUND_CVE_2025_0647 331 332#if WORKAROUND_CVE_2025_0647 333func cortex_a710_impl_defined_el3_handler 334 mov x0, #WA_LS_RCG_EN 335 336 /* See if this call came from trap handler. */ 337 cmp x1, #EC_IMP_DEF_EL3 338 bne wa_cve_2025_0647_do_cpp_wa 339 orr x0, x0, #WA_IS_TRAP_HANDLER 340 b wa_cve_2025_0647_do_cpp_wa 341endfunc cortex_a710_impl_defined_el3_handler 342#endif 343 344 /* ---------------------------------------------------- 345 * HW will do the cache maintenance while powering down 346 * ---------------------------------------------------- 347 */ 348func cortex_a710_core_pwr_dwn 349 apply_erratum cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768 350 apply_erratum cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219, NO_GET_CPU_REV 351 352 /* --------------------------------------------------- 353 * Enable CPU power down bit in power control register 354 * --------------------------------------------------- 355 */ 356 sysreg_bit_set CORTEX_A710_CPUPWRCTLR_EL1, CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 357 apply_erratum cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515, NO_GET_CPU_REV 358 isb 359 ret 360endfunc cortex_a710_core_pwr_dwn 361 362cpu_reset_func_start cortex_a710 363 /* Disable speculative loads */ 364 msr SSBS, xzr 365 apply_erratum cortex_a710, ERRATUM(3324338), ERRATA_A710_3324338 366 367 enable_mpmm 368cpu_reset_func_end cortex_a710 369 370 /* --------------------------------------------- 371 * This function provides Cortex-A710 specific 372 * register information for crash reporting. 373 * It needs to return with x6 pointing to 374 * a list of register names in ascii and 375 * x8 - x15 having values of registers to be 376 * reported. 377 * --------------------------------------------- 378 */ 379.section .rodata.cortex_a710_regs, "aS" 380cortex_a710_regs: /* The ascii list of register names to be reported */ 381 .asciz "cpuectlr_el1", "" 382 383func cortex_a710_cpu_reg_dump 384 adr x6, cortex_a710_regs 385 mrs x8, CORTEX_A710_CPUECTLR_EL1 386 ret 387endfunc cortex_a710_cpu_reg_dump 388 389#if WORKAROUND_CVE_2025_0647 && IMAGE_BL31 390declare_cpu_ops_eh cortex_a710, CORTEX_A710_MIDR, \ 391 cortex_a710_reset_func, \ 392 cortex_a710_impl_defined_el3_handler, \ 393 cortex_a710_core_pwr_dwn 394#else 395declare_cpu_ops cortex_a710, CORTEX_A710_MIDR, \ 396 cortex_a710_reset_func, \ 397 cortex_a710_core_pwr_dwn 398#endif 399