1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a710.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex A710 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25.global check_erratum_cortex_a710_3701772 26 27#if WORKAROUND_CVE_2022_23960 28 wa_cve_2022_23960_bhb_vector_table CORTEX_A710_BHB_LOOP_COUNT, cortex_a710 29#endif /* WORKAROUND_CVE_2022_23960 */ 30 31/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 32workaround_reset_start cortex_a710, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 33 sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, BIT(46) 34workaround_reset_end cortex_a710, CVE(2024, 5660) 35 36check_erratum_ls cortex_a710, CVE(2024, 5660), CPU_REV(2, 1) 37 38workaround_reset_start cortex_a710, ERRATUM(1987031), ERRATA_A710_1987031 39 ldr x0,=0x6 40 msr S3_6_c15_c8_0,x0 41 ldr x0,=0xF3A08002 42 msr S3_6_c15_c8_2,x0 43 ldr x0,=0xFFF0F7FE 44 msr S3_6_c15_c8_3,x0 45 ldr x0,=0x40000001003ff 46 msr S3_6_c15_c8_1,x0 47 ldr x0,=0x7 48 msr S3_6_c15_c8_0,x0 49 ldr x0,=0xBF200000 50 msr S3_6_c15_c8_2,x0 51 ldr x0,=0xFFEF0000 52 msr S3_6_c15_c8_3,x0 53 ldr x0,=0x40000001003f3 54 msr S3_6_c15_c8_1,x0 55workaround_reset_end cortex_a710, ERRATUM(1987031) 56 57check_erratum_ls cortex_a710, ERRATUM(1987031), CPU_REV(2, 0) 58 59workaround_runtime_start cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768 60 /* Stash ERRSELR_EL1 in x2 */ 61 mrs x2, ERRSELR_EL1 62 63 /* Select error record 0 and clear ED bit */ 64 msr ERRSELR_EL1, xzr 65 mrs x1, ERXCTLR_EL1 66 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 67 msr ERXCTLR_EL1, x1 68 69 /* Select error record 1 and clear ED bit */ 70 mov x0, #1 71 msr ERRSELR_EL1, x0 72 mrs x1, ERXCTLR_EL1 73 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 74 msr ERXCTLR_EL1, x1 75 76 /* Restore ERRSELR_EL1 from x2 */ 77 msr ERRSELR_EL1, x2 78workaround_runtime_end cortex_a710, ERRATUM(2008768), NO_ISB 79 80check_erratum_ls cortex_a710, ERRATUM(2008768), CPU_REV(2, 0) 81 82workaround_reset_start cortex_a710, ERRATUM(2017096), ERRATA_A710_2017096 83 sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT 84workaround_reset_end cortex_a710, ERRATUM(2017096) 85 86check_erratum_ls cortex_a710, ERRATUM(2017096), CPU_REV(2, 0) 87 88workaround_reset_start cortex_a710, ERRATUM(2055002), ERRATA_A710_2055002 89 sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_46 90workaround_reset_end cortex_a710, ERRATUM(2055002) 91 92check_erratum_range cortex_a710, ERRATUM(2055002), CPU_REV(1, 0), CPU_REV(2, 0) 93 94workaround_reset_start cortex_a710, ERRATUM(2058056), ERRATA_A710_2058056 95 sysreg_bitfield_insert CORTEX_A710_CPUECTLR2_EL1, CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV, \ 96 CPUECTLR2_EL1_PF_MODE_LSB, CPUECTLR2_EL1_PF_MODE_WIDTH 97workaround_reset_end cortex_a710, ERRATUM(2058056) 98 99check_erratum_ls cortex_a710, ERRATUM(2058056), CPU_REV(2, 1) 100 101workaround_reset_start cortex_a710, ERRATUM(2081180), ERRATA_A710_2081180 102 ldr x0,=0x3 103 msr S3_6_c15_c8_0,x0 104 ldr x0,=0xF3A08002 105 msr S3_6_c15_c8_2,x0 106 ldr x0,=0xFFF0F7FE 107 msr S3_6_c15_c8_3,x0 108 ldr x0,=0x10002001003FF 109 msr S3_6_c15_c8_1,x0 110 ldr x0,=0x4 111 msr S3_6_c15_c8_0,x0 112 ldr x0,=0xBF200000 113 msr S3_6_c15_c8_2,x0 114 ldr x0,=0xFFEF0000 115 msr S3_6_c15_c8_3,x0 116 ldr x0,=0x10002001003F3 117 msr S3_6_c15_c8_1,x0 118workaround_reset_end cortex_a710, ERRATUM(2081180) 119 120check_erratum_ls cortex_a710, ERRATUM(2081180), CPU_REV(2, 0) 121 122workaround_reset_start cortex_a710, ERRATUM(2083908), ERRATA_A710_2083908 123 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_13 124workaround_reset_end cortex_a710, ERRATUM(2083908) 125 126check_erratum_range cortex_a710, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0) 127 128workaround_reset_start cortex_a710, ERRATUM(2136059), ERRATA_A710_2136059 129 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_44 130workaround_reset_end cortex_a710, ERRATUM(2136059) 131 132check_erratum_ls cortex_a710, ERRATUM(2136059), CPU_REV(2, 0) 133 134workaround_reset_start cortex_a710, ERRATUM(2147715), ERRATA_A710_2147715 135 sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22 136workaround_reset_end cortex_a710, ERRATUM(2147715) 137 138check_erratum_range cortex_a710, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0) 139 140workaround_reset_start cortex_a710, ERRATUM(2216384), ERRATA_A710_2216384 141 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_17 142 143 ldr x0,=0x5 144 msr CORTEX_A710_CPUPSELR_EL3, x0 145 ldr x0,=0x10F600E000 146 msr CORTEX_A710_CPUPOR_EL3, x0 147 ldr x0,=0x10FF80E000 148 msr CORTEX_A710_CPUPMR_EL3, x0 149 ldr x0,=0x80000000003FF 150 msr CORTEX_A710_CPUPCR_EL3, x0 151workaround_reset_end cortex_a710, ERRATUM(2216384) 152 153check_erratum_ls cortex_a710, ERRATUM(2216384), CPU_REV(2, 0) 154 155workaround_reset_start cortex_a710, ERRATUM(2267065), ERRATA_A710_2267065 156 sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22 157workaround_reset_end cortex_a710, ERRATUM(2267065) 158 159check_erratum_ls cortex_a710, ERRATUM(2267065), CPU_REV(2, 0) 160 161workaround_reset_start cortex_a710, ERRATUM(2282622), ERRATA_A710_2282622 162 sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, BIT(0) 163workaround_reset_end cortex_a710, ERRATUM(2282622) 164 165check_erratum_ls cortex_a710, ERRATUM(2282622), CPU_REV(2, 1) 166 167.global erratum_cortex_a710_2291219_wa 168workaround_runtime_start cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219 169 /* Set/unset bit 36 in ACTLR2_EL1. The first call will set it, applying 170 * the workaround. Second call clears it to undo it. */ 171 sysreg_bit_toggle CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_36 172workaround_runtime_end cortex_a710, ERRATUM(2291219), NO_ISB 173 174check_erratum_ls cortex_a710, ERRATUM(2291219), CPU_REV(2, 0) 175 176/* 177 * ERRATA_DSU_2313941 is defined in dsu_helpers.S but applies to Cortex-A710 as 178 * well. Create a symbollic link to existing errata workaround to get them 179 * registered under the Errata Framework. 180 */ 181.equ check_erratum_cortex_a710_2313941, check_errata_dsu_2313941 182.equ erratum_cortex_a710_2313941_wa, errata_dsu_2313941_wa 183add_erratum_entry cortex_a710, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET 184 185workaround_reset_start cortex_a710, ERRATUM(2371105), ERRATA_A710_2371105 186 /* Set bit 40 in CPUACTLR2_EL1 */ 187 sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_40 188workaround_reset_end cortex_a710, ERRATUM(2371105) 189 190check_erratum_ls cortex_a710, ERRATUM(2371105), CPU_REV(2, 0) 191 192workaround_reset_start cortex_a710, ERRATUM(2742423), ERRATA_A710_2742423 193 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 194 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, BIT(55) 195 sysreg_bit_clear CORTEX_A710_CPUACTLR5_EL1, BIT(56) 196workaround_reset_end cortex_a710, ERRATUM(2742423) 197 198check_erratum_ls cortex_a710, ERRATUM(2742423), CPU_REV(2, 1) 199 200workaround_runtime_start cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515 201 /* dsb before isb of power down sequence */ 202 dsb sy 203workaround_runtime_end cortex_a710, ERRATUM(2768515), NO_ISB 204 205check_erratum_ls cortex_a710, ERRATUM(2768515), CPU_REV(2, 1) 206 207workaround_reset_start cortex_a710, ERRATUM(2778471), ERRATA_A710_2778471 208 sysreg_bit_set CORTEX_A710_CPUACTLR3_EL1, BIT(47) 209workaround_reset_end cortex_a710, ERRATUM(2778471) 210 211check_erratum_ls cortex_a710, ERRATUM(2778471), CPU_REV(2, 1) 212 213workaround_reset_start cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 214#if IMAGE_BL31 215 /* 216 * The Cortex-A710 generic vectors are overridden to apply errata 217 * mitigation on exception entry from lower ELs. 218 */ 219 override_vector_table wa_cve_vbar_cortex_a710 220#endif /* IMAGE_BL31 */ 221workaround_reset_end cortex_a710, CVE(2022, 23960) 222 223check_erratum_chosen cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 224 225add_erratum_entry cortex_a710, ERRATUM(3701772), ERRATA_A710_3701772, NO_APPLY_AT_RESET 226 227check_erratum_ls cortex_a710, ERRATUM(3701772), CPU_REV(2, 1) 228 229 /* ---------------------------------------------------- 230 * HW will do the cache maintenance while powering down 231 * ---------------------------------------------------- 232 */ 233func cortex_a710_core_pwr_dwn 234 apply_erratum cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768, NO_GET_CPU_REV 235 apply_erratum cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219, NO_GET_CPU_REV 236 237 /* --------------------------------------------------- 238 * Enable CPU power down bit in power control register 239 * --------------------------------------------------- 240 */ 241 sysreg_bit_set CORTEX_A710_CPUPWRCTLR_EL1, CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 242 apply_erratum cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515, NO_GET_CPU_REV 243 isb 244 ret 245endfunc cortex_a710_core_pwr_dwn 246 247cpu_reset_func_start cortex_a710 248 /* Disable speculative loads */ 249 msr SSBS, xzr 250cpu_reset_func_end cortex_a710 251 252 /* --------------------------------------------- 253 * This function provides Cortex-A710 specific 254 * register information for crash reporting. 255 * It needs to return with x6 pointing to 256 * a list of register names in ascii and 257 * x8 - x15 having values of registers to be 258 * reported. 259 * --------------------------------------------- 260 */ 261.section .rodata.cortex_a710_regs, "aS" 262cortex_a710_regs: /* The ascii list of register names to be reported */ 263 .asciz "cpuectlr_el1", "" 264 265func cortex_a710_cpu_reg_dump 266 adr x6, cortex_a710_regs 267 mrs x8, CORTEX_A710_CPUECTLR_EL1 268 ret 269endfunc cortex_a710_cpu_reg_dump 270 271declare_cpu_ops cortex_a710, CORTEX_A710_MIDR, \ 272 cortex_a710_reset_func, \ 273 cortex_a710_core_pwr_dwn 274