1/* 2 * Copyright (c) 2021-2022, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a710.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex A710 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_A710_BHB_LOOP_COUNT, cortex_a710 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29/* -------------------------------------------------- 30 * Errata Workaround for Cortex-A710 Erratum 1987031. 31 * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710. It is still 32 * open. 33 * Inputs: 34 * x0: variant[4:7] and revision[0:3] of current cpu. 35 * Shall clobber: x0-x17 36 * -------------------------------------------------- 37 */ 38func errata_a710_1987031_wa 39 /* Check revision. */ 40 mov x17, x30 41 bl check_errata_1987031 42 cbz x0, 1f 43 44 /* Apply instruction patching sequence */ 45 ldr x0,=0x6 46 msr S3_6_c15_c8_0,x0 47 ldr x0,=0xF3A08002 48 msr S3_6_c15_c8_2,x0 49 ldr x0,=0xFFF0F7FE 50 msr S3_6_c15_c8_3,x0 51 ldr x0,=0x40000001003ff 52 msr S3_6_c15_c8_1,x0 53 ldr x0,=0x7 54 msr S3_6_c15_c8_0,x0 55 ldr x0,=0xBF200000 56 msr S3_6_c15_c8_2,x0 57 ldr x0,=0xFFEF0000 58 msr S3_6_c15_c8_3,x0 59 ldr x0,=0x40000001003f3 60 msr S3_6_c15_c8_1,x0 61 isb 621: 63 ret x17 64endfunc errata_a710_1987031_wa 65 66func check_errata_1987031 67 /* Applies to r0p0, r1p0 and r2p0 */ 68 mov x1, #0x20 69 b cpu_rev_var_ls 70endfunc check_errata_1987031 71 72/* -------------------------------------------------- 73 * Errata Workaround for Cortex-A710 Erratum 2081180. 74 * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710. 75 * It is still open. 76 * Inputs: 77 * x0: variant[4:7] and revision[0:3] of current cpu. 78 * Shall clobber: x0-x17 79 * -------------------------------------------------- 80 */ 81func errata_a710_2081180_wa 82 /* Check revision. */ 83 mov x17, x30 84 bl check_errata_2081180 85 cbz x0, 1f 86 87 /* Apply instruction patching sequence */ 88 ldr x0,=0x3 89 msr S3_6_c15_c8_0,x0 90 ldr x0,=0xF3A08002 91 msr S3_6_c15_c8_2,x0 92 ldr x0,=0xFFF0F7FE 93 msr S3_6_c15_c8_3,x0 94 ldr x0,=0x10002001003FF 95 msr S3_6_c15_c8_1,x0 96 ldr x0,=0x4 97 msr S3_6_c15_c8_0,x0 98 ldr x0,=0xBF200000 99 msr S3_6_c15_c8_2,x0 100 ldr x0,=0xFFEF0000 101 msr S3_6_c15_c8_3,x0 102 ldr x0,=0x10002001003F3 103 msr S3_6_c15_c8_1,x0 104 isb 1051: 106 ret x17 107endfunc errata_a710_2081180_wa 108 109func check_errata_2081180 110 /* Applies to r0p0, r1p0 and r2p0 */ 111 mov x1, #0x20 112 b cpu_rev_var_ls 113endfunc check_errata_2081180 114 115/* --------------------------------------------------------------------- 116 * Errata Workaround for Cortex-A710 Erratum 2055002. 117 * This applies to revision r1p0, r2p0 of Cortex-A710 and is still open. 118 * Inputs: 119 * x0: variant[4:7] and revision[0:3] of current cpu. 120 * Shall clobber: x0-x17 121 * --------------------------------------------------------------------- 122 */ 123func errata_a710_2055002_wa 124 /* Compare x0 against revision r2p0 */ 125 mov x17, x30 126 bl check_errata_2055002 127 cbz x0, 1f 128 mrs x1, CORTEX_A710_CPUACTLR_EL1 129 orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_46 130 msr CORTEX_A710_CPUACTLR_EL1, x1 1311: 132 ret x17 133endfunc errata_a710_2055002_wa 134 135func check_errata_2055002 136 /* Applies to r1p0, r2p0 */ 137 mov x1, #0x20 138 b cpu_rev_var_ls 139endfunc check_errata_2055002 140 141/* ------------------------------------------------------------- 142 * Errata Workaround for Cortex-A710 Erratum 2017096. 143 * This applies to revisions r0p0, r1p0 and r2p0 of Cortex-A710. 144 * Inputs: 145 * x0: variant[4:7] and revision[0:3] of current cpu. 146 * Shall clobber: x0-x17 147 * ------------------------------------------------------------- 148 */ 149func errata_a710_2017096_wa 150 /* Compare x0 against revision r0p0 to r2p0 */ 151 mov x17, x30 152 bl check_errata_2017096 153 cbz x0, 1f 154 mrs x1, CORTEX_A710_CPUECTLR_EL1 155 orr x1, x1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT 156 msr CORTEX_A710_CPUECTLR_EL1, x1 157 1581: 159 ret x17 160endfunc errata_a710_2017096_wa 161 162func check_errata_2017096 163 /* Applies to r0p0, r1p0, r2p0 */ 164 mov x1, #0x20 165 b cpu_rev_var_ls 166endfunc check_errata_2017096 167 168 169/* --------------------------------------------------------------------- 170 * Errata Workaround for Cortex-A710 Erratum 2083908. 171 * This applies to revision r2p0 of Cortex-A710 and is still open. 172 * Inputs: 173 * x0: variant[4:7] and revision[0:3] of current cpu. 174 * Shall clobber: x0-x17 175 * --------------------------------------------------------------------- 176 */ 177func errata_a710_2083908_wa 178 /* Compare x0 against revision r2p0 */ 179 mov x17, x30 180 bl check_errata_2083908 181 cbz x0, 1f 182 mrs x1, CORTEX_A710_CPUACTLR5_EL1 183 orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_13 184 msr CORTEX_A710_CPUACTLR5_EL1, x1 1851: 186 ret x17 187endfunc errata_a710_2083908_wa 188 189func check_errata_2083908 190 /* Applies to r2p0 */ 191 mov x1, #CPU_REV(2, 0) 192 mov x2, #CPU_REV(2, 0) 193 b cpu_rev_var_range 194endfunc check_errata_2083908 195 196/* --------------------------------------------------------------------- 197 * Errata Workaround for Cortex-A710 Erratum 2058056. 198 * This applies to revisions r0p0, r1p0 and r2p0 of Cortex-A710 and is still 199 * open. 200 * Inputs: 201 * x0: variant[4:7] and revision[0:3] of current cpu. 202 * Shall clobber: x0-x17 203 * --------------------------------------------------------------------- 204 */ 205func errata_a710_2058056_wa 206 /* Compare x0 against revision r2p0 */ 207 mov x17, x30 208 bl check_errata_2058056 209 cbz x0, 1f 210 mrs x1, CORTEX_A710_CPUECTLR2_EL1 211 mov x0, #CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV 212 bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH 213 msr CORTEX_A710_CPUECTLR2_EL1, x1 2141: 215 ret x17 216endfunc errata_a710_2058056_wa 217 218func check_errata_2058056 219 /* Applies to r0p0, r1p0 and r2p0 */ 220 mov x1, #0x20 221 b cpu_rev_var_ls 222endfunc check_errata_2058056 223 224/* -------------------------------------------------- 225 * Errata Workaround for Cortex-A710 Erratum 2267065. 226 * This applies to revisions r0p0, r1p0 and r2p0. 227 * It is fixed in r2p1. 228 * Inputs: 229 * x0: variant[4:7] and revision[0:3] of current cpu. 230 * Shall clobber: x0-x1, x17 231 * -------------------------------------------------- 232 */ 233func errata_a710_2267065_wa 234 /* Compare x0 against revision r2p0 */ 235 mov x17, x30 236 bl check_errata_2267065 237 cbz x0, 1f 238 239 /* Apply instruction patching sequence */ 240 mrs x1, CORTEX_A710_CPUACTLR_EL1 241 orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_22 242 msr CORTEX_A710_CPUACTLR_EL1, x1 2431: 244 ret x17 245endfunc errata_a710_2267065_wa 246 247func check_errata_2267065 248 /* Applies to r0p0, r1p0 and r2p0 */ 249 mov x1, #0x20 250 b cpu_rev_var_ls 251endfunc check_errata_2267065 252 253/* --------------------------------------------------------------- 254 * Errata Workaround for Cortex-A710 Erratum 2136059. 255 * This applies to revision r0p0, r1p0 and r2p0. 256 * It is fixed in r2p1. 257 * Inputs: 258 * x0: variant[4:7] and revision[0:3] of current cpu. 259 * Shall clobber: x0-x17 260 * --------------------------------------------------------------- 261 */ 262func errata_a710_2136059_wa 263 /* Compare x0 against revision r2p0 */ 264 mov x17, x30 265 bl check_errata_2136059 266 cbz x0, 1f 267 268 /* Apply the workaround */ 269 mrs x1, CORTEX_A710_CPUACTLR5_EL1 270 orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_44 271 msr CORTEX_A710_CPUACTLR5_EL1, x1 272 2731: 274 ret x17 275endfunc errata_a710_2136059_wa 276 277func check_errata_2136059 278 /* Applies to r0p0, r1p0 and r2p0 */ 279 mov x1, #0x20 280 b cpu_rev_var_ls 281endfunc check_errata_2136059 282 283/* ---------------------------------------------------------------- 284 * Errata workaround for Cortex-A710 Erratum 2147715. 285 * This applies to revision r2p0, and is fixed in r2p1. 286 * Inputs: 287 * x0: variant[4:7] and revision[0:3] of current cpu. 288 * Shall clobber: x0, x1, x17 289 * ---------------------------------------------------------------- 290 */ 291func errata_a710_2147715_wa 292 mov x17, x30 293 bl check_errata_2147715 294 cbz x0, 1f 295 296 /* Apply workaround; set CPUACTLR_EL1[22] 297 * to 1, which will cause the CFP instruction 298 * to invalidate all branch predictor resources 299 * regardless of context. 300 */ 301 mrs x1, CORTEX_A710_CPUACTLR_EL1 302 orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_22 303 msr CORTEX_A710_CPUACTLR_EL1, x1 3041: 305 ret x17 306endfunc errata_a710_2147715_wa 307 308func check_errata_2147715 309 mov x1, #0x20 310 mov x2, #0x20 311 b cpu_rev_var_range 312endfunc check_errata_2147715 313 314/* --------------------------------------------------------------- 315 * Errata Workaround for Cortex-A710 Erratum 2216384. 316 * This applies to revision r0p0, r1p0 and r2p0. 317 * It is fixed in r2p1. 318 * Inputs: 319 * x0: variant[4:7] and revision[0:3] of current cpu. 320 * Shall clobber: x0-x17 321 * --------------------------------------------------------------- 322 */ 323func errata_a710_2216384_wa 324 /* Compare x0 against revision r2p0 */ 325 mov x17, x30 326 bl check_errata_2216384 327 cbz x0, 1f 328 329 /* Apply workaround: set CPUACTLR5_EL1[17] 330 * to 1 and the following instruction 331 * patching sequence. 332 */ 333 mrs x1, CORTEX_A710_CPUACTLR5_EL1 334 orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_17 335 msr CORTEX_A710_CPUACTLR5_EL1, x1 336 337 ldr x0,=0x5 338 msr CORTEX_A710_CPUPSELR_EL3, x0 339 ldr x0,=0x10F600E000 340 msr CORTEX_A710_CPUPOR_EL3, x0 341 ldr x0,=0x10FF80E000 342 msr CORTEX_A710_CPUPMR_EL3, x0 343 ldr x0,=0x80000000003FF 344 msr CORTEX_A710_CPUPCR_EL3, x0 345 isb 3461: 347 ret x17 348endfunc errata_a710_2216384_wa 349 350func check_errata_2216384 351 /* Applies to r0p0, r1p0 and r2p0 */ 352 mov x1, #0x20 353 b cpu_rev_var_ls 354endfunc check_errata_2216384 355 356/* --------------------------------------------------------------- 357 * Errata Workaround for Cortex-A710 Erratum 2282622. 358 * This applies to revision r0p0, r1p0 and r2p0. 359 * It is fixed in r2p1. 360 * Inputs: 361 * x0: variant[4:7] and revision[0:3] of current cpu. 362 * Shall clobber: x0, x1, x17 363 * --------------------------------------------------------------- 364 */ 365func errata_a710_2282622_wa 366 /* Compare x0 against revision r2p0 */ 367 mov x17, x30 368 bl check_errata_2282622 369 cbz x0, 1f 370 371 /* Apply the workaround */ 372 mrs x1, CORTEX_A710_CPUACTLR2_EL1 373 orr x1, x1, BIT(0) 374 msr CORTEX_A710_CPUACTLR2_EL1, x1 375 3761: 377 ret x17 378endfunc errata_a710_2282622_wa 379 380func check_errata_2282622 381 /* Applies to r0p0, r1p0 and r2p0 */ 382 mov x1, #0x20 383 b cpu_rev_var_ls 384endfunc check_errata_2282622 385 386/* --------------------------------------------------------------- 387 * Errata Workaround for Cortex-A710 Erratum 2008768. 388 * This applies to revision r0p0, r1p0 and r2p0. 389 * It is fixed in r2p1. 390 * Inputs: 391 * x0: variant[4:7] and revision[0:3] of current cpu. 392 * Shall clobber: x0, x1, x2, x17 393 * --------------------------------------------------------------- 394 */ 395func errata_a710_2008768_wa 396 mov x17, x30 397 bl check_errata_2008768 398 cbz x0, 1f 399 400 /* Stash ERRSELR_EL1 in x2 */ 401 mrs x2, ERRSELR_EL1 402 403 /* Select error record 0 and clear ED bit */ 404 msr ERRSELR_EL1, xzr 405 mrs x1, ERXCTLR_EL1 406 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 407 msr ERXCTLR_EL1, x1 408 409 /* Select error record 1 and clear ED bit */ 410 mov x0, #1 411 msr ERRSELR_EL1, x0 412 mrs x1, ERXCTLR_EL1 413 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 414 msr ERXCTLR_EL1, x1 415 416 /* Restore ERRSELR_EL1 from x2 */ 417 msr ERRSELR_EL1, x2 418 4191: 420 ret x17 421endfunc errata_a710_2008768_wa 422 423func check_errata_2008768 424 /* Applies to r0p0, r1p0 and r2p0 */ 425 mov x1, #0x20 426 b cpu_rev_var_ls 427endfunc check_errata_2008768 428 429/* ------------------------------------------------------- 430 * Errata Workaround for Cortex-A710 Erratum 2371105. 431 * This applies to revisions <= r2p0 and is fixed in r2p1. 432 * x0: variant[4:7] and revision[0:3] of current cpu. 433 * Shall clobber: x0-x17 434 * ------------------------------------------------------- 435 */ 436func errata_a710_2371105_wa 437 /* Check workaround compatibility. */ 438 mov x17, x30 439 bl check_errata_2371105 440 cbz x0, 1f 441 442 /* Set bit 40 in CPUACTLR2_EL1 */ 443 mrs x1, CORTEX_A710_CPUACTLR2_EL1 444 orr x1, x1, #CORTEX_A710_CPUACTLR2_EL1_BIT_40 445 msr CORTEX_A710_CPUACTLR2_EL1, x1 446 isb 4471: 448 ret x17 449endfunc errata_a710_2371105_wa 450 451func check_errata_2371105 452 /* Applies to <= r2p0. */ 453 mov x1, #0x20 454 b cpu_rev_var_ls 455endfunc check_errata_2371105 456 457func check_errata_cve_2022_23960 458#if WORKAROUND_CVE_2022_23960 459 mov x0, #ERRATA_APPLIES 460#else 461 mov x0, #ERRATA_MISSING 462#endif 463 ret 464endfunc check_errata_cve_2022_23960 465 466 /* ---------------------------------------------------- 467 * HW will do the cache maintenance while powering down 468 * ---------------------------------------------------- 469 */ 470func cortex_a710_core_pwr_dwn 471 472#if ERRATA_A710_2008768 473 mov x4, x30 474 bl cpu_get_rev_var 475 bl errata_a710_2008768_wa 476 mov x30, x4 477#endif 478 479 /* --------------------------------------------------- 480 * Enable CPU power down bit in power control register 481 * --------------------------------------------------- 482 */ 483 mrs x0, CORTEX_A710_CPUPWRCTLR_EL1 484 orr x0, x0, #CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 485 msr CORTEX_A710_CPUPWRCTLR_EL1, x0 486 isb 487 ret 488endfunc cortex_a710_core_pwr_dwn 489 490#if REPORT_ERRATA 491 /* 492 * Errata printing function for Cortex-A710. Must follow AAPCS. 493 */ 494func cortex_a710_errata_report 495 stp x8, x30, [sp, #-16]! 496 497 bl cpu_get_rev_var 498 mov x8, x0 499 500 /* 501 * Report all errata. The revision-variant information is passed to 502 * checking functions of each errata. 503 */ 504 report_errata ERRATA_A710_1987031, cortex_a710, 1987031 505 report_errata ERRATA_A710_2081180, cortex_a710, 2081180 506 report_errata ERRATA_A710_2055002, cortex_a710, 2055002 507 report_errata ERRATA_A710_2017096, cortex_a710, 2017096 508 report_errata ERRATA_A710_2083908, cortex_a710, 2083908 509 report_errata ERRATA_A710_2058056, cortex_a710, 2058056 510 report_errata ERRATA_A710_2267065, cortex_a710, 2267065 511 report_errata ERRATA_A710_2136059, cortex_a710, 2136059 512 report_errata ERRATA_A710_2282622, cortex_a710, 2282622 513 report_errata ERRATA_A710_2008768, cortex_a710, 2008768 514 report_errata ERRATA_A710_2147715, cortex_a710, 2147715 515 report_errata ERRATA_A710_2216384, cortex_a710, 2216384 516 report_errata ERRATA_A710_2371105, cortex_a710, 2371105 517 report_errata WORKAROUND_CVE_2022_23960, cortex_a710, cve_2022_23960 518 report_errata ERRATA_DSU_2313941, cortex_a710, dsu_2313941 519 520 ldp x8, x30, [sp], #16 521 ret 522endfunc cortex_a710_errata_report 523#endif 524 525func cortex_a710_reset_func 526 mov x19, x30 527 528 /* Disable speculative loads */ 529 msr SSBS, xzr 530 531 bl cpu_get_rev_var 532 mov x18, x0 533 534#if ERRATA_DSU_2313941 535 bl errata_dsu_2313941_wa 536#endif 537 538#if ERRATA_A710_1987031 539 mov x0, x18 540 bl errata_a710_1987031_wa 541#endif 542 543#if ERRATA_A710_2081180 544 mov x0, x18 545 bl errata_a710_2081180_wa 546#endif 547 548#if ERRATA_A710_2055002 549 mov x0, x18 550 bl errata_a710_2055002_wa 551#endif 552 553#if ERRATA_A710_2017096 554 mov x0, x18 555 bl errata_a710_2017096_wa 556#endif 557 558#if ERRATA_A710_2083908 559 mov x0, x18 560 bl errata_a710_2083908_wa 561#endif 562 563#if ERRATA_A710_2058056 564 mov x0, x18 565 bl errata_a710_2058056_wa 566#endif 567 568#if ERRATA_A710_2267065 569 mov x0, x18 570 bl errata_a710_2267065_wa 571#endif 572 573#if ERRATA_A710_2136059 574 mov x0, x18 575 bl errata_a710_2136059_wa 576#endif 577 578#if ERRATA_A710_2147715 579 mov x0, x18 580 bl errata_a710_2147715_wa 581#endif 582 583#if ERRATA_A710_2216384 584 mov x0, x18 585 bl errata_a710_2216384_wa 586#endif /* ERRATA_A710_2216384 */ 587 588#if ERRATA_A710_2282622 589 mov x0, x18 590 bl errata_a710_2282622_wa 591#endif 592 593#if ERRATA_A710_2371105 594 mov x0, x18 595 bl errata_a710_2371105_wa 596#endif 597 598#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 599 /* 600 * The Cortex-A710 generic vectors are overridden to apply errata 601 * mitigation on exception entry from lower ELs. 602 */ 603 adr x0, wa_cve_vbar_cortex_a710 604 msr vbar_el3, x0 605#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ 606 607 isb 608 ret x19 609endfunc cortex_a710_reset_func 610 611 /* --------------------------------------------- 612 * This function provides Cortex-A710 specific 613 * register information for crash reporting. 614 * It needs to return with x6 pointing to 615 * a list of register names in ascii and 616 * x8 - x15 having values of registers to be 617 * reported. 618 * --------------------------------------------- 619 */ 620.section .rodata.cortex_a710_regs, "aS" 621cortex_a710_regs: /* The ascii list of register names to be reported */ 622 .asciz "cpuectlr_el1", "" 623 624func cortex_a710_cpu_reg_dump 625 adr x6, cortex_a710_regs 626 mrs x8, CORTEX_A710_CPUECTLR_EL1 627 ret 628endfunc cortex_a710_cpu_reg_dump 629 630declare_cpu_ops cortex_a710, CORTEX_A710_MIDR, \ 631 cortex_a710_reset_func, \ 632 cortex_a710_core_pwr_dwn 633