1/* 2 * Copyright (c) 2021, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a710.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex A710 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24/* -------------------------------------------------- 25 * Errata Workaround for Cortex-A710 Erratum 1987031. 26 * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710. It is still 27 * open. 28 * Inputs: 29 * x0: variant[4:7] and revision[0:3] of current cpu. 30 * Shall clobber: x0-x17 31 * -------------------------------------------------- 32 */ 33func errata_a710_1987031_wa 34 /* Check revision. */ 35 mov x17, x30 36 bl check_errata_1987031 37 cbz x0, 1f 38 39 /* Apply instruction patching sequence */ 40 ldr x0,=0x6 41 msr S3_6_c15_c8_0,x0 42 ldr x0,=0xF3A08002 43 msr S3_6_c15_c8_2,x0 44 ldr x0,=0xFFF0F7FE 45 msr S3_6_c15_c8_3,x0 46 ldr x0,=0x40000001003ff 47 msr S3_6_c15_c8_1,x0 48 ldr x0,=0x7 49 msr S3_6_c15_c8_0,x0 50 ldr x0,=0xBF200000 51 msr S3_6_c15_c8_2,x0 52 ldr x0,=0xFFEF0000 53 msr S3_6_c15_c8_3,x0 54 ldr x0,=0x40000001003f3 55 msr S3_6_c15_c8_1,x0 56 isb 571: 58 ret x17 59endfunc errata_a710_1987031_wa 60 61func check_errata_1987031 62 /* Applies to r0p0, r1p0 and r2p0 */ 63 mov x1, #0x20 64 b cpu_rev_var_ls 65endfunc check_errata_1987031 66 67/* -------------------------------------------------- 68 * Errata Workaround for Cortex-A710 Erratum 2081180. 69 * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710. 70 * It is still open. 71 * Inputs: 72 * x0: variant[4:7] and revision[0:3] of current cpu. 73 * Shall clobber: x0-x17 74 * -------------------------------------------------- 75 */ 76func errata_a710_2081180_wa 77 /* Check revision. */ 78 mov x17, x30 79 bl check_errata_2081180 80 cbz x0, 1f 81 82 /* Apply instruction patching sequence */ 83 ldr x0,=0x3 84 msr S3_6_c15_c8_0,x0 85 ldr x0,=0xF3A08002 86 msr S3_6_c15_c8_2,x0 87 ldr x0,=0xFFF0F7FE 88 msr S3_6_c15_c8_3,x0 89 ldr x0,=0x10002001003FF 90 msr S3_6_c15_c8_1,x0 91 ldr x0,=0x4 92 msr S3_6_c15_c8_0,x0 93 ldr x0,=0xBF200000 94 msr S3_6_c15_c8_2,x0 95 ldr x0,=0xFFEF0000 96 msr S3_6_c15_c8_3,x0 97 ldr x0,=0x10002001003F3 98 msr S3_6_c15_c8_1,x0 99 isb 1001: 101 ret x17 102endfunc errata_a710_2081180_wa 103 104func check_errata_2081180 105 /* Applies to r0p0, r1p0 and r2p0 */ 106 mov x1, #0x20 107 b cpu_rev_var_ls 108endfunc check_errata_2081180 109 110/* --------------------------------------------------------------------- 111 * Errata Workaround for Cortex-A710 Erratum 2055002. 112 * This applies to revision r1p0, r2p0 of Cortex-A710 and is still open. 113 * Inputs: 114 * x0: variant[4:7] and revision[0:3] of current cpu. 115 * Shall clobber: x0-x17 116 * --------------------------------------------------------------------- 117 */ 118func errata_a710_2055002_wa 119 /* Compare x0 against revision r2p0 */ 120 mov x17, x30 121 bl check_errata_2055002 122 cbz x0, 1f 123 mrs x1, CORTEX_A710_CPUACTLR_EL1 124 orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_46 125 msr CORTEX_A710_CPUACTLR_EL1, x1 1261: 127 ret x17 128endfunc errata_a710_2055002_wa 129 130func check_errata_2055002 131 /* Applies to r1p0, r2p0 */ 132 mov x1, #0x20 133 b cpu_rev_var_ls 134endfunc check_errata_2055002 135 136/* ------------------------------------------------------------- 137 * Errata Workaround for Cortex-A710 Erratum 2017096. 138 * This applies to revisions r0p0, r1p0 and r2p0 of Cortex-A710. 139 * Inputs: 140 * x0: variant[4:7] and revision[0:3] of current cpu. 141 * Shall clobber: x0-x17 142 * ------------------------------------------------------------- 143 */ 144func errata_a710_2017096_wa 145 /* Compare x0 against revision r0p0 to r2p0 */ 146 mov x17, x30 147 bl check_errata_2017096 148 cbz x0, 1f 149 mrs x1, CORTEX_A710_CPUECTLR_EL1 150 orr x1, x1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT 151 msr CORTEX_A710_CPUECTLR_EL1, x1 152 1531: 154 ret x17 155endfunc errata_a710_2017096_wa 156 157func check_errata_2017096 158 /* Applies to r0p0, r1p0, r2p0 */ 159 mov x1, #0x20 160 b cpu_rev_var_ls 161endfunc check_errata_2017096 162 163 164/* --------------------------------------------------------------------- 165 * Errata Workaround for Cortex-A710 Erratum 2083908. 166 * This applies to revision r2p0 of Cortex-A710 and is still open. 167 * Inputs: 168 * x0: variant[4:7] and revision[0:3] of current cpu. 169 * Shall clobber: x0-x17 170 * --------------------------------------------------------------------- 171 */ 172func errata_a710_2083908_wa 173 /* Compare x0 against revision r2p0 */ 174 mov x17, x30 175 bl check_errata_2083908 176 cbz x0, 1f 177 mrs x1, CORTEX_A710_CPUACTLR5_EL1 178 orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_13 179 msr CORTEX_A710_CPUACTLR5_EL1, x1 1801: 181 ret x17 182endfunc errata_a710_2083908_wa 183 184func check_errata_2083908 185 /* Applies to r2p0 */ 186 mov x1, #CPU_REV(2, 0) 187 mov x2, #CPU_REV(2, 0) 188 b cpu_rev_var_range 189endfunc check_errata_2083908 190 191/* --------------------------------------------------------------------- 192 * Errata Workaround for Cortex-A710 Erratum 2058056. 193 * This applies to revisions r0p0, r1p0 and r2p0 of Cortex-A710 and is still 194 * open. 195 * Inputs: 196 * x0: variant[4:7] and revision[0:3] of current cpu. 197 * Shall clobber: x0-x17 198 * --------------------------------------------------------------------- 199 */ 200func errata_a710_2058056_wa 201 /* Compare x0 against revision r2p0 */ 202 mov x17, x30 203 bl check_errata_2058056 204 cbz x0, 1f 205 mrs x1, CORTEX_A710_CPUECTLR2_EL1 206 mov x0, #CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV 207 bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH 208 msr CORTEX_A710_CPUECTLR2_EL1, x1 2091: 210 ret x17 211endfunc errata_a710_2058056_wa 212 213func check_errata_2058056 214 /* Applies to r0p0, r1p0 and r2p0 */ 215 mov x1, #0x20 216 b cpu_rev_var_ls 217endfunc check_errata_2058056 218 219/* -------------------------------------------------- 220 * Errata Workaround for Cortex-A710 Erratum 2267065. 221 * This applies to revisions r0p0, r1p0 and r2p0. 222 * It is fixed in r2p1. 223 * Inputs: 224 * x0: variant[4:7] and revision[0:3] of current cpu. 225 * Shall clobber: x0-x1, x17 226 * -------------------------------------------------- 227 */ 228func errata_a710_2267065_wa 229 /* Compare x0 against revision r2p0 */ 230 mov x17, x30 231 bl check_errata_2267065 232 cbz x0, 1f 233 234 /* Apply instruction patching sequence */ 235 mrs x1, CORTEX_A710_CPUACTLR_EL1 236 orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_22 237 msr CORTEX_A710_CPUACTLR_EL1, x1 2381: 239 ret x17 240endfunc errata_a710_2267065_wa 241 242func check_errata_2267065 243 /* Applies to r0p0, r1p0 and r2p0 */ 244 mov x1, #0x20 245 b cpu_rev_var_ls 246endfunc check_errata_2267065 247 248/* --------------------------------------------------------------- 249 * Errata Workaround for Cortex-A710 Erratum 2136059. 250 * This applies to revision r0p0, r1p0 and r2p0. 251 * It is fixed in r2p1. 252 * Inputs: 253 * x0: variant[4:7] and revision[0:3] of current cpu. 254 * Shall clobber: x0-x17 255 * --------------------------------------------------------------- 256 */ 257func errata_a710_2136059_wa 258 /* Compare x0 against revision r2p0 */ 259 mov x17, x30 260 bl check_errata_2136059 261 cbz x0, 1f 262 263 /* Apply the workaround */ 264 mrs x1, CORTEX_A710_CPUACTLR5_EL1 265 orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_44 266 msr CORTEX_A710_CPUACTLR5_EL1, x1 267 2681: 269 ret x17 270endfunc errata_a710_2136059_wa 271 272func check_errata_2136059 273 /* Applies to r0p0, r1p0 and r2p0 */ 274 mov x1, #0x20 275 b cpu_rev_var_ls 276endfunc check_errata_2136059 277 278 /* ---------------------------------------------------- 279 * HW will do the cache maintenance while powering down 280 * ---------------------------------------------------- 281 */ 282func cortex_a710_core_pwr_dwn 283 /* --------------------------------------------------- 284 * Enable CPU power down bit in power control register 285 * --------------------------------------------------- 286 */ 287 mrs x0, CORTEX_A710_CPUPWRCTLR_EL1 288 orr x0, x0, #CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 289 msr CORTEX_A710_CPUPWRCTLR_EL1, x0 290 isb 291 ret 292endfunc cortex_a710_core_pwr_dwn 293 294#if REPORT_ERRATA 295 /* 296 * Errata printing function for Cortex-A710. Must follow AAPCS. 297 */ 298func cortex_a710_errata_report 299 stp x8, x30, [sp, #-16]! 300 301 bl cpu_get_rev_var 302 mov x8, x0 303 304 /* 305 * Report all errata. The revision-variant information is passed to 306 * checking functions of each errata. 307 */ 308 report_errata ERRATA_A710_1987031, cortex_a710, 1987031 309 report_errata ERRATA_A710_2081180, cortex_a710, 2081180 310 report_errata ERRATA_A710_2055002, cortex_a710, 2055002 311 report_errata ERRATA_A710_2017096, cortex_a710, 2017096 312 report_errata ERRATA_A710_2083908, cortex_a710, 2083908 313 report_errata ERRATA_A710_2058056, cortex_a710, 2058056 314 report_errata ERRATA_A710_2267065, cortex_a710, 2267065 315 report_errata ERRATA_A710_2136059, cortex_a710, 2136059 316 317 ldp x8, x30, [sp], #16 318 ret 319endfunc cortex_a710_errata_report 320#endif 321 322func cortex_a710_reset_func 323 mov x19, x30 324 325 /* Disable speculative loads */ 326 msr SSBS, xzr 327 328 bl cpu_get_rev_var 329 mov x18, x0 330 331#if ERRATA_A710_1987031 332 mov x0, x18 333 bl errata_a710_1987031_wa 334#endif 335 336#if ERRATA_A710_2081180 337 mov x0, x18 338 bl errata_a710_2081180_wa 339#endif 340 341#if ERRATA_A710_2055002 342 mov x0, x18 343 bl errata_a710_2055002_wa 344#endif 345 346#if ERRATA_A710_2017096 347 mov x0, x18 348 bl errata_a710_2017096_wa 349#endif 350 351#if ERRATA_A710_2083908 352 mov x0, x18 353 bl errata_a710_2083908_wa 354#endif 355 356#if ERRATA_A710_2058056 357 mov x0, x18 358 bl errata_a710_2058056_wa 359#endif 360 361#if ERRATA_A710_2267065 362 mov x0, x18 363 bl errata_a710_2267065_wa 364#endif 365 366#if ERRATA_A710_2136059 367 mov x0, x18 368 bl errata_a710_2136059_wa 369#endif 370 371 isb 372 ret x19 373endfunc cortex_a710_reset_func 374 375 /* --------------------------------------------- 376 * This function provides Cortex-A710 specific 377 * register information for crash reporting. 378 * It needs to return with x6 pointing to 379 * a list of register names in ascii and 380 * x8 - x15 having values of registers to be 381 * reported. 382 * --------------------------------------------- 383 */ 384.section .rodata.cortex_a710_regs, "aS" 385cortex_a710_regs: /* The ascii list of register names to be reported */ 386 .asciz "cpuectlr_el1", "" 387 388func cortex_a710_cpu_reg_dump 389 adr x6, cortex_a710_regs 390 mrs x8, CORTEX_A710_CPUECTLR_EL1 391 ret 392endfunc cortex_a710_cpu_reg_dump 393 394declare_cpu_ops cortex_a710, CORTEX_A710_MIDR, \ 395 cortex_a710_reset_func, \ 396 cortex_a710_core_pwr_dwn 397