1/* 2 * Copyright (c) 2021-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a710.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex A710 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_A710_BHB_LOOP_COUNT, cortex_a710 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 30workaround_reset_start cortex_a710, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 31 sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, BIT(46) 32workaround_reset_end cortex_a710, CVE(2024, 5660) 33 34check_erratum_ls cortex_a710, CVE(2024, 5660), CPU_REV(2, 1) 35 36workaround_reset_start cortex_a710, ERRATUM(1987031), ERRATA_A710_1987031 37 ldr x0,=0x6 38 msr S3_6_c15_c8_0,x0 39 ldr x0,=0xF3A08002 40 msr S3_6_c15_c8_2,x0 41 ldr x0,=0xFFF0F7FE 42 msr S3_6_c15_c8_3,x0 43 ldr x0,=0x40000001003ff 44 msr S3_6_c15_c8_1,x0 45 ldr x0,=0x7 46 msr S3_6_c15_c8_0,x0 47 ldr x0,=0xBF200000 48 msr S3_6_c15_c8_2,x0 49 ldr x0,=0xFFEF0000 50 msr S3_6_c15_c8_3,x0 51 ldr x0,=0x40000001003f3 52 msr S3_6_c15_c8_1,x0 53workaround_reset_end cortex_a710, ERRATUM(1987031) 54 55check_erratum_ls cortex_a710, ERRATUM(1987031), CPU_REV(2, 0) 56 57workaround_runtime_start cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768 58 /* Stash ERRSELR_EL1 in x2 */ 59 mrs x2, ERRSELR_EL1 60 61 /* Select error record 0 and clear ED bit */ 62 msr ERRSELR_EL1, xzr 63 mrs x1, ERXCTLR_EL1 64 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 65 msr ERXCTLR_EL1, x1 66 67 /* Select error record 1 and clear ED bit */ 68 mov x0, #1 69 msr ERRSELR_EL1, x0 70 mrs x1, ERXCTLR_EL1 71 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 72 msr ERXCTLR_EL1, x1 73 74 /* Restore ERRSELR_EL1 from x2 */ 75 msr ERRSELR_EL1, x2 76workaround_runtime_end cortex_a710, ERRATUM(2008768), NO_ISB 77 78check_erratum_ls cortex_a710, ERRATUM(2008768), CPU_REV(2, 0) 79 80workaround_reset_start cortex_a710, ERRATUM(2017096), ERRATA_A710_2017096 81 sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT 82workaround_reset_end cortex_a710, ERRATUM(2017096) 83 84check_erratum_ls cortex_a710, ERRATUM(2017096), CPU_REV(2, 0) 85 86workaround_reset_start cortex_a710, ERRATUM(2055002), ERRATA_A710_2055002 87 sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_46 88workaround_reset_end cortex_a710, ERRATUM(2055002) 89 90check_erratum_range cortex_a710, ERRATUM(2055002), CPU_REV(1, 0), CPU_REV(2, 0) 91 92workaround_reset_start cortex_a710, ERRATUM(2058056), ERRATA_A710_2058056 93 sysreg_bitfield_insert CORTEX_A710_CPUECTLR2_EL1, CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV, \ 94 CPUECTLR2_EL1_PF_MODE_LSB, CPUECTLR2_EL1_PF_MODE_WIDTH 95workaround_reset_end cortex_a710, ERRATUM(2058056) 96 97check_erratum_ls cortex_a710, ERRATUM(2058056), CPU_REV(2, 1) 98 99workaround_reset_start cortex_a710, ERRATUM(2081180), ERRATA_A710_2081180 100 ldr x0,=0x3 101 msr S3_6_c15_c8_0,x0 102 ldr x0,=0xF3A08002 103 msr S3_6_c15_c8_2,x0 104 ldr x0,=0xFFF0F7FE 105 msr S3_6_c15_c8_3,x0 106 ldr x0,=0x10002001003FF 107 msr S3_6_c15_c8_1,x0 108 ldr x0,=0x4 109 msr S3_6_c15_c8_0,x0 110 ldr x0,=0xBF200000 111 msr S3_6_c15_c8_2,x0 112 ldr x0,=0xFFEF0000 113 msr S3_6_c15_c8_3,x0 114 ldr x0,=0x10002001003F3 115 msr S3_6_c15_c8_1,x0 116workaround_reset_end cortex_a710, ERRATUM(2081180) 117 118check_erratum_ls cortex_a710, ERRATUM(2081180), CPU_REV(2, 0) 119 120workaround_reset_start cortex_a710, ERRATUM(2083908), ERRATA_A710_2083908 121 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_13 122workaround_reset_end cortex_a710, ERRATUM(2083908) 123 124check_erratum_range cortex_a710, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0) 125 126workaround_reset_start cortex_a710, ERRATUM(2136059), ERRATA_A710_2136059 127 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_44 128workaround_reset_end cortex_a710, ERRATUM(2136059) 129 130check_erratum_ls cortex_a710, ERRATUM(2136059), CPU_REV(2, 0) 131 132workaround_reset_start cortex_a710, ERRATUM(2147715), ERRATA_A710_2147715 133 sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22 134workaround_reset_end cortex_a710, ERRATUM(2147715) 135 136check_erratum_range cortex_a710, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0) 137 138workaround_reset_start cortex_a710, ERRATUM(2216384), ERRATA_A710_2216384 139 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_17 140 141 ldr x0,=0x5 142 msr CORTEX_A710_CPUPSELR_EL3, x0 143 ldr x0,=0x10F600E000 144 msr CORTEX_A710_CPUPOR_EL3, x0 145 ldr x0,=0x10FF80E000 146 msr CORTEX_A710_CPUPMR_EL3, x0 147 ldr x0,=0x80000000003FF 148 msr CORTEX_A710_CPUPCR_EL3, x0 149workaround_reset_end cortex_a710, ERRATUM(2216384) 150 151check_erratum_ls cortex_a710, ERRATUM(2216384), CPU_REV(2, 0) 152 153workaround_reset_start cortex_a710, ERRATUM(2267065), ERRATA_A710_2267065 154 sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22 155workaround_reset_end cortex_a710, ERRATUM(2267065) 156 157check_erratum_ls cortex_a710, ERRATUM(2267065), CPU_REV(2, 0) 158 159workaround_reset_start cortex_a710, ERRATUM(2282622), ERRATA_A710_2282622 160 sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, BIT(0) 161workaround_reset_end cortex_a710, ERRATUM(2282622) 162 163check_erratum_ls cortex_a710, ERRATUM(2282622), CPU_REV(2, 1) 164 165workaround_runtime_start cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219 166 /* Set bit 36 in ACTLR2_EL1 */ 167 sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_36 168workaround_runtime_end cortex_a710, ERRATUM(2291219), NO_ISB 169 170check_erratum_ls cortex_a710, ERRATUM(2291219), CPU_REV(2, 0) 171 172/* 173 * ERRATA_DSU_2313941 is defined in dsu_helpers.S but applies to Cortex-A710 as 174 * well. Create a symbollic link to existing errata workaround to get them 175 * registered under the Errata Framework. 176 */ 177.equ check_erratum_cortex_a710_2313941, check_errata_dsu_2313941 178.equ erratum_cortex_a710_2313941_wa, errata_dsu_2313941_wa 179add_erratum_entry cortex_a710, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET 180 181workaround_reset_start cortex_a710, ERRATUM(2371105), ERRATA_A710_2371105 182 /* Set bit 40 in CPUACTLR2_EL1 */ 183 sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_40 184workaround_reset_end cortex_a710, ERRATUM(2371105) 185 186check_erratum_ls cortex_a710, ERRATUM(2371105), CPU_REV(2, 0) 187 188workaround_reset_start cortex_a710, ERRATUM(2742423), ERRATA_A710_2742423 189 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 190 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, BIT(55) 191 sysreg_bit_clear CORTEX_A710_CPUACTLR5_EL1, BIT(56) 192workaround_reset_end cortex_a710, ERRATUM(2742423) 193 194check_erratum_ls cortex_a710, ERRATUM(2742423), CPU_REV(2, 1) 195 196workaround_runtime_start cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515 197 /* dsb before isb of power down sequence */ 198 dsb sy 199workaround_runtime_end cortex_a710, ERRATUM(2768515), NO_ISB 200 201check_erratum_ls cortex_a710, ERRATUM(2768515), CPU_REV(2, 1) 202 203workaround_reset_start cortex_a710, ERRATUM(2778471), ERRATA_A710_2778471 204 sysreg_bit_set CORTEX_A710_CPUACTLR3_EL1, BIT(47) 205workaround_reset_end cortex_a710, ERRATUM(2778471) 206 207check_erratum_ls cortex_a710, ERRATUM(2778471), CPU_REV(2, 1) 208 209workaround_reset_start cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 210#if IMAGE_BL31 211 /* 212 * The Cortex-A710 generic vectors are overridden to apply errata 213 * mitigation on exception entry from lower ELs. 214 */ 215 override_vector_table wa_cve_vbar_cortex_a710 216#endif /* IMAGE_BL31 */ 217workaround_reset_end cortex_a710, CVE(2022, 23960) 218 219check_erratum_chosen cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 220 221 /* ---------------------------------------------------- 222 * HW will do the cache maintenance while powering down 223 * ---------------------------------------------------- 224 */ 225func cortex_a710_core_pwr_dwn 226 apply_erratum cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768, NO_GET_CPU_REV 227 apply_erratum cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219, NO_GET_CPU_REV 228 229 /* --------------------------------------------------- 230 * Enable CPU power down bit in power control register 231 * --------------------------------------------------- 232 */ 233 sysreg_bit_set CORTEX_A710_CPUPWRCTLR_EL1, CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 234 apply_erratum cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515, NO_GET_CPU_REV 235 isb 236 ret 237endfunc cortex_a710_core_pwr_dwn 238 239cpu_reset_func_start cortex_a710 240 /* Disable speculative loads */ 241 msr SSBS, xzr 242cpu_reset_func_end cortex_a710 243 244 /* --------------------------------------------- 245 * This function provides Cortex-A710 specific 246 * register information for crash reporting. 247 * It needs to return with x6 pointing to 248 * a list of register names in ascii and 249 * x8 - x15 having values of registers to be 250 * reported. 251 * --------------------------------------------- 252 */ 253.section .rodata.cortex_a710_regs, "aS" 254cortex_a710_regs: /* The ascii list of register names to be reported */ 255 .asciz "cpuectlr_el1", "" 256 257func cortex_a710_cpu_reg_dump 258 adr x6, cortex_a710_regs 259 mrs x8, CORTEX_A710_CPUECTLR_EL1 260 ret 261endfunc cortex_a710_cpu_reg_dump 262 263declare_cpu_ops cortex_a710, CORTEX_A710_MIDR, \ 264 cortex_a710_reset_func, \ 265 cortex_a710_core_pwr_dwn 266