1/* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30#include <arch.h> 31#include <asm_macros.S> 32#include <assert_macros.S> 33#include <bl_common.h> 34#include <cortex_a57.h> 35#include <cpu_macros.S> 36#include <plat_macros.S> 37 38 /* --------------------------------------------- 39 * Disable L1 data cache and unified L2 cache 40 * --------------------------------------------- 41 */ 42func cortex_a57_disable_dcache 43 mrs x1, sctlr_el3 44 bic x1, x1, #SCTLR_C_BIT 45 msr sctlr_el3, x1 46 isb 47 ret 48endfunc cortex_a57_disable_dcache 49 50 /* --------------------------------------------- 51 * Disable all types of L2 prefetches. 52 * --------------------------------------------- 53 */ 54func cortex_a57_disable_l2_prefetch 55 mrs x0, CPUECTLR_EL1 56 orr x0, x0, #CPUECTLR_DIS_TWD_ACC_PFTCH_BIT 57 mov x1, #CPUECTLR_L2_IPFTCH_DIST_MASK 58 orr x1, x1, #CPUECTLR_L2_DPFTCH_DIST_MASK 59 bic x0, x0, x1 60 msr CPUECTLR_EL1, x0 61 isb 62 dsb ish 63 ret 64endfunc cortex_a57_disable_l2_prefetch 65 66 /* --------------------------------------------- 67 * Disable intra-cluster coherency 68 * --------------------------------------------- 69 */ 70func cortex_a57_disable_smp 71 mrs x0, CPUECTLR_EL1 72 bic x0, x0, #CPUECTLR_SMP_BIT 73 msr CPUECTLR_EL1, x0 74 ret 75endfunc cortex_a57_disable_smp 76 77 /* --------------------------------------------- 78 * Disable debug interfaces 79 * --------------------------------------------- 80 */ 81func cortex_a57_disable_ext_debug 82 mov x0, #1 83 msr osdlr_el1, x0 84 isb 85 dsb sy 86 ret 87endfunc cortex_a57_disable_ext_debug 88 89 /* -------------------------------------------------- 90 * Errata Workaround for Cortex A57 Errata #806969. 91 * This applies only to revision r0p0 of Cortex A57. 92 * Inputs: 93 * x0: variant[4:7] and revision[0:3] of current cpu. 94 * Clobbers : x0 - x5 95 * -------------------------------------------------- 96 */ 97func errata_a57_806969_wa 98 /* 99 * Compare x0 against revision r0p0 100 */ 101 cbz x0, apply_806969 102#if DEBUG 103 b print_revision_warning 104#else 105 ret 106#endif 107apply_806969: 108 mrs x1, CPUACTLR_EL1 109 orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA 110 msr CPUACTLR_EL1, x1 111 ret 112endfunc errata_a57_806969_wa 113 114 115 /* --------------------------------------------------- 116 * Errata Workaround for Cortex A57 Errata #813420. 117 * This applies only to revision r0p0 of Cortex A57. 118 * Inputs: 119 * x0: variant[4:7] and revision[0:3] of current cpu. 120 * Clobbers : x0 - x5 121 * --------------------------------------------------- 122 */ 123func errata_a57_813420_wa 124 /* 125 * Compare x0 against revision r0p0 126 */ 127 cbz x0, apply_813420 128#if DEBUG 129 b print_revision_warning 130#else 131 ret 132#endif 133apply_813420: 134 mrs x1, CPUACTLR_EL1 135 orr x1, x1, #CPUACTLR_DCC_AS_DCCI 136 msr CPUACTLR_EL1, x1 137 ret 138endfunc errata_a57_813420_wa 139 140 /* -------------------------------------------------------------------- 141 * Disable the over-read from the LDNP instruction. 142 * 143 * This applies to all revisions <= r1p2. The performance degradation 144 * observed with LDNP/STNP has been fixed on r1p3 and onwards. 145 * 146 * Inputs: 147 * x0: variant[4:7] and revision[0:3] of current cpu. 148 * Clobbers : x0 - x5, x30 149 * --------------------------------------------------------------------- 150 */ 151func a57_disable_ldnp_overread 152 /* 153 * Compare x0 against revision r1p2 154 */ 155 cmp x0, #0x12 156 b.ls disable_hint 157#if DEBUG 158 b print_revision_warning 159#else 160 ret 161#endif 162disable_hint: 163 mrs x1, CPUACTLR_EL1 164 orr x1, x1, #CPUACTLR_DIS_OVERREAD 165 msr CPUACTLR_EL1, x1 166 ret 167endfunc a57_disable_ldnp_overread 168 169 /* ------------------------------------------------- 170 * The CPU Ops reset function for Cortex-A57. 171 * Clobbers: x0-x5, x15, x19, x30 172 * ------------------------------------------------- 173 */ 174func cortex_a57_reset_func 175 mov x19, x30 176 mrs x0, midr_el1 177 178 /* 179 * Extract the variant[20:23] and revision[0:3] from x0 180 * and pack it in x15[0:7] as variant[4:7] and revision[0:3]. 181 * First extract x0[16:23] to x15[0:7] and zero fill the rest. 182 * Then extract x0[0:3] into x15[0:3] retaining other bits. 183 */ 184 ubfx x15, x0, #(MIDR_VAR_SHIFT - MIDR_REV_BITS), #(MIDR_REV_BITS + MIDR_VAR_BITS) 185 bfxil x15, x0, #MIDR_REV_SHIFT, #MIDR_REV_BITS 186 187#if ERRATA_A57_806969 188 mov x0, x15 189 bl errata_a57_806969_wa 190#endif 191 192#if ERRATA_A57_813420 193 mov x0, x15 194 bl errata_a57_813420_wa 195#endif 196 197#if A57_DISABLE_NON_TEMPORAL_HINT 198 mov x0, x15 199 bl a57_disable_ldnp_overread 200#endif 201 202 /* --------------------------------------------- 203 * Enable the SMP bit. 204 * --------------------------------------------- 205 */ 206 mrs x0, CPUECTLR_EL1 207 orr x0, x0, #CPUECTLR_SMP_BIT 208 msr CPUECTLR_EL1, x0 209 isb 210 ret x19 211endfunc cortex_a57_reset_func 212 213 /* ---------------------------------------------------- 214 * The CPU Ops core power down function for Cortex-A57. 215 * ---------------------------------------------------- 216 */ 217func cortex_a57_core_pwr_dwn 218 mov x18, x30 219 220 /* --------------------------------------------- 221 * Turn off caches. 222 * --------------------------------------------- 223 */ 224 bl cortex_a57_disable_dcache 225 226 /* --------------------------------------------- 227 * Disable the L2 prefetches. 228 * --------------------------------------------- 229 */ 230 bl cortex_a57_disable_l2_prefetch 231 232 /* --------------------------------------------- 233 * Flush L1 caches. 234 * --------------------------------------------- 235 */ 236 mov x0, #DCCISW 237 bl dcsw_op_level1 238 239 /* --------------------------------------------- 240 * Come out of intra cluster coherency 241 * --------------------------------------------- 242 */ 243 bl cortex_a57_disable_smp 244 245 /* --------------------------------------------- 246 * Force the debug interfaces to be quiescent 247 * --------------------------------------------- 248 */ 249 mov x30, x18 250 b cortex_a57_disable_ext_debug 251endfunc cortex_a57_core_pwr_dwn 252 253 /* ------------------------------------------------------- 254 * The CPU Ops cluster power down function for Cortex-A57. 255 * ------------------------------------------------------- 256 */ 257func cortex_a57_cluster_pwr_dwn 258 mov x18, x30 259 260 /* --------------------------------------------- 261 * Turn off caches. 262 * --------------------------------------------- 263 */ 264 bl cortex_a57_disable_dcache 265 266 /* --------------------------------------------- 267 * Disable the L2 prefetches. 268 * --------------------------------------------- 269 */ 270 bl cortex_a57_disable_l2_prefetch 271 272#if !SKIP_A57_L1_FLUSH_PWR_DWN 273 /* ------------------------------------------------- 274 * Flush the L1 caches. 275 * ------------------------------------------------- 276 */ 277 mov x0, #DCCISW 278 bl dcsw_op_level1 279#endif 280 /* --------------------------------------------- 281 * Disable the optional ACP. 282 * --------------------------------------------- 283 */ 284 bl plat_disable_acp 285 286 /* ------------------------------------------------- 287 * Flush the L2 caches. 288 * ------------------------------------------------- 289 */ 290 mov x0, #DCCISW 291 bl dcsw_op_level2 292 293 /* --------------------------------------------- 294 * Come out of intra cluster coherency 295 * --------------------------------------------- 296 */ 297 bl cortex_a57_disable_smp 298 299 /* --------------------------------------------- 300 * Force the debug interfaces to be quiescent 301 * --------------------------------------------- 302 */ 303 mov x30, x18 304 b cortex_a57_disable_ext_debug 305endfunc cortex_a57_cluster_pwr_dwn 306 307 /* --------------------------------------------- 308 * This function provides cortex_a57 specific 309 * register information for crash reporting. 310 * It needs to return with x6 pointing to 311 * a list of register names in ascii and 312 * x8 - x15 having values of registers to be 313 * reported. 314 * --------------------------------------------- 315 */ 316.section .rodata.cortex_a57_regs, "aS" 317cortex_a57_regs: /* The ascii list of register names to be reported */ 318 .asciz "cpuectlr_el1", "" 319 320func cortex_a57_cpu_reg_dump 321 adr x6, cortex_a57_regs 322 mrs x8, CPUECTLR_EL1 323 ret 324endfunc cortex_a57_cpu_reg_dump 325 326 327declare_cpu_ops cortex_a57, CORTEX_A57_MIDR 328