1/* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30#include <arch.h> 31#include <asm_macros.S> 32#include <assert_macros.S> 33#include <bl_common.h> 34#include <cortex_a57.h> 35#include <cpu_macros.S> 36#include <debug.h> 37#include <plat_macros.S> 38 39 /* --------------------------------------------- 40 * Disable L1 data cache and unified L2 cache 41 * --------------------------------------------- 42 */ 43func cortex_a57_disable_dcache 44 mrs x1, sctlr_el3 45 bic x1, x1, #SCTLR_C_BIT 46 msr sctlr_el3, x1 47 isb 48 ret 49endfunc cortex_a57_disable_dcache 50 51 /* --------------------------------------------- 52 * Disable all types of L2 prefetches. 53 * --------------------------------------------- 54 */ 55func cortex_a57_disable_l2_prefetch 56 mrs x0, CPUECTLR_EL1 57 orr x0, x0, #CPUECTLR_DIS_TWD_ACC_PFTCH_BIT 58 mov x1, #CPUECTLR_L2_IPFTCH_DIST_MASK 59 orr x1, x1, #CPUECTLR_L2_DPFTCH_DIST_MASK 60 bic x0, x0, x1 61 msr CPUECTLR_EL1, x0 62 isb 63 dsb ish 64 ret 65endfunc cortex_a57_disable_l2_prefetch 66 67 /* --------------------------------------------- 68 * Disable intra-cluster coherency 69 * --------------------------------------------- 70 */ 71func cortex_a57_disable_smp 72 mrs x0, CPUECTLR_EL1 73 bic x0, x0, #CPUECTLR_SMP_BIT 74 msr CPUECTLR_EL1, x0 75 ret 76endfunc cortex_a57_disable_smp 77 78 /* --------------------------------------------- 79 * Disable debug interfaces 80 * --------------------------------------------- 81 */ 82func cortex_a57_disable_ext_debug 83 mov x0, #1 84 msr osdlr_el1, x0 85 isb 86 dsb sy 87 ret 88endfunc cortex_a57_disable_ext_debug 89 90 /* -------------------------------------------------- 91 * Errata Workaround for Cortex A57 Errata #806969. 92 * This applies only to revision r0p0 of Cortex A57. 93 * Inputs: 94 * x0: variant[4:7] and revision[0:3] of current cpu. 95 * Clobbers : x0 - x5 96 * -------------------------------------------------- 97 */ 98func errata_a57_806969_wa 99 /* 100 * Compare x0 against revision r0p0 101 */ 102 cbz x0, apply_806969 103#if LOG_LEVEL >= LOG_LEVEL_VERBOSE 104 b print_revision_warning 105#else 106 ret 107#endif 108apply_806969: 109 mrs x1, CPUACTLR_EL1 110 orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA 111 msr CPUACTLR_EL1, x1 112 ret 113endfunc errata_a57_806969_wa 114 115 116 /* --------------------------------------------------- 117 * Errata Workaround for Cortex A57 Errata #813420. 118 * This applies only to revision r0p0 of Cortex A57. 119 * Inputs: 120 * x0: variant[4:7] and revision[0:3] of current cpu. 121 * Clobbers : x0 - x5 122 * --------------------------------------------------- 123 */ 124func errata_a57_813420_wa 125 /* 126 * Compare x0 against revision r0p0 127 */ 128 cbz x0, apply_813420 129#if LOG_LEVEL >= LOG_LEVEL_VERBOSE 130 b print_revision_warning 131#else 132 ret 133#endif 134apply_813420: 135 mrs x1, CPUACTLR_EL1 136 orr x1, x1, #CPUACTLR_DCC_AS_DCCI 137 msr CPUACTLR_EL1, x1 138 ret 139endfunc errata_a57_813420_wa 140 141 /* -------------------------------------------------------------------- 142 * Disable the over-read from the LDNP instruction. 143 * 144 * This applies to all revisions <= r1p2. The performance degradation 145 * observed with LDNP/STNP has been fixed on r1p3 and onwards. 146 * 147 * Inputs: 148 * x0: variant[4:7] and revision[0:3] of current cpu. 149 * Clobbers : x0 - x5, x30 150 * --------------------------------------------------------------------- 151 */ 152func a57_disable_ldnp_overread 153 /* 154 * Compare x0 against revision r1p2 155 */ 156 cmp x0, #0x12 157 b.ls disable_hint 158#if LOG_LEVEL >= LOG_LEVEL_VERBOSE 159 b print_revision_warning 160#else 161 ret 162#endif 163disable_hint: 164 mrs x1, CPUACTLR_EL1 165 orr x1, x1, #CPUACTLR_DIS_OVERREAD 166 msr CPUACTLR_EL1, x1 167 ret 168endfunc a57_disable_ldnp_overread 169 170 /* ------------------------------------------------- 171 * The CPU Ops reset function for Cortex-A57. 172 * Clobbers: x0-x5, x15, x19, x30 173 * ------------------------------------------------- 174 */ 175func cortex_a57_reset_func 176 mov x19, x30 177 mrs x0, midr_el1 178 179 /* 180 * Extract the variant[20:23] and revision[0:3] from x0 181 * and pack it in x15[0:7] as variant[4:7] and revision[0:3]. 182 * First extract x0[16:23] to x15[0:7] and zero fill the rest. 183 * Then extract x0[0:3] into x15[0:3] retaining other bits. 184 */ 185 ubfx x15, x0, #(MIDR_VAR_SHIFT - MIDR_REV_BITS), #(MIDR_REV_BITS + MIDR_VAR_BITS) 186 bfxil x15, x0, #MIDR_REV_SHIFT, #MIDR_REV_BITS 187 188#if ERRATA_A57_806969 189 mov x0, x15 190 bl errata_a57_806969_wa 191#endif 192 193#if ERRATA_A57_813420 194 mov x0, x15 195 bl errata_a57_813420_wa 196#endif 197 198#if A57_DISABLE_NON_TEMPORAL_HINT 199 mov x0, x15 200 bl a57_disable_ldnp_overread 201#endif 202 203 /* --------------------------------------------- 204 * Enable the SMP bit. 205 * --------------------------------------------- 206 */ 207 mrs x0, CPUECTLR_EL1 208 orr x0, x0, #CPUECTLR_SMP_BIT 209 msr CPUECTLR_EL1, x0 210 isb 211 ret x19 212endfunc cortex_a57_reset_func 213 214 /* ---------------------------------------------------- 215 * The CPU Ops core power down function for Cortex-A57. 216 * ---------------------------------------------------- 217 */ 218func cortex_a57_core_pwr_dwn 219 mov x18, x30 220 221 /* --------------------------------------------- 222 * Turn off caches. 223 * --------------------------------------------- 224 */ 225 bl cortex_a57_disable_dcache 226 227 /* --------------------------------------------- 228 * Disable the L2 prefetches. 229 * --------------------------------------------- 230 */ 231 bl cortex_a57_disable_l2_prefetch 232 233 /* --------------------------------------------- 234 * Flush L1 caches. 235 * --------------------------------------------- 236 */ 237 mov x0, #DCCISW 238 bl dcsw_op_level1 239 240 /* --------------------------------------------- 241 * Come out of intra cluster coherency 242 * --------------------------------------------- 243 */ 244 bl cortex_a57_disable_smp 245 246 /* --------------------------------------------- 247 * Force the debug interfaces to be quiescent 248 * --------------------------------------------- 249 */ 250 mov x30, x18 251 b cortex_a57_disable_ext_debug 252endfunc cortex_a57_core_pwr_dwn 253 254 /* ------------------------------------------------------- 255 * The CPU Ops cluster power down function for Cortex-A57. 256 * ------------------------------------------------------- 257 */ 258func cortex_a57_cluster_pwr_dwn 259 mov x18, x30 260 261 /* --------------------------------------------- 262 * Turn off caches. 263 * --------------------------------------------- 264 */ 265 bl cortex_a57_disable_dcache 266 267 /* --------------------------------------------- 268 * Disable the L2 prefetches. 269 * --------------------------------------------- 270 */ 271 bl cortex_a57_disable_l2_prefetch 272 273#if !SKIP_A57_L1_FLUSH_PWR_DWN 274 /* ------------------------------------------------- 275 * Flush the L1 caches. 276 * ------------------------------------------------- 277 */ 278 mov x0, #DCCISW 279 bl dcsw_op_level1 280#endif 281 /* --------------------------------------------- 282 * Disable the optional ACP. 283 * --------------------------------------------- 284 */ 285 bl plat_disable_acp 286 287 /* ------------------------------------------------- 288 * Flush the L2 caches. 289 * ------------------------------------------------- 290 */ 291 mov x0, #DCCISW 292 bl dcsw_op_level2 293 294 /* --------------------------------------------- 295 * Come out of intra cluster coherency 296 * --------------------------------------------- 297 */ 298 bl cortex_a57_disable_smp 299 300 /* --------------------------------------------- 301 * Force the debug interfaces to be quiescent 302 * --------------------------------------------- 303 */ 304 mov x30, x18 305 b cortex_a57_disable_ext_debug 306endfunc cortex_a57_cluster_pwr_dwn 307 308 /* --------------------------------------------- 309 * This function provides cortex_a57 specific 310 * register information for crash reporting. 311 * It needs to return with x6 pointing to 312 * a list of register names in ascii and 313 * x8 - x15 having values of registers to be 314 * reported. 315 * --------------------------------------------- 316 */ 317.section .rodata.cortex_a57_regs, "aS" 318cortex_a57_regs: /* The ascii list of register names to be reported */ 319 .asciz "cpuectlr_el1", "" 320 321func cortex_a57_cpu_reg_dump 322 adr x6, cortex_a57_regs 323 mrs x8, CPUECTLR_EL1 324 ret 325endfunc cortex_a57_cpu_reg_dump 326 327 328declare_cpu_ops cortex_a57, CORTEX_A57_MIDR 329