1/* 2 * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <assert_macros.S> 9#include <common/bl_common.h> 10#include <common/debug.h> 11#include <cortex_a57.h> 12#include <cpu_macros.S> 13#include <plat_macros.S> 14 15 /* --------------------------------------------- 16 * Disable L1 data cache and unified L2 cache 17 * --------------------------------------------- 18 */ 19func cortex_a57_disable_dcache 20 mrs x1, sctlr_el3 21 bic x1, x1, #SCTLR_C_BIT 22 msr sctlr_el3, x1 23 isb 24 ret 25endfunc cortex_a57_disable_dcache 26 27 /* --------------------------------------------- 28 * Disable all types of L2 prefetches. 29 * --------------------------------------------- 30 */ 31func cortex_a57_disable_l2_prefetch 32 mrs x0, CORTEX_A57_ECTLR_EL1 33 orr x0, x0, #CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT 34 mov x1, #CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK 35 orr x1, x1, #CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK 36 bic x0, x0, x1 37 msr CORTEX_A57_ECTLR_EL1, x0 38 isb 39 dsb ish 40 ret 41endfunc cortex_a57_disable_l2_prefetch 42 43 /* --------------------------------------------- 44 * Disable intra-cluster coherency 45 * --------------------------------------------- 46 */ 47func cortex_a57_disable_smp 48 mrs x0, CORTEX_A57_ECTLR_EL1 49 bic x0, x0, #CORTEX_A57_ECTLR_SMP_BIT 50 msr CORTEX_A57_ECTLR_EL1, x0 51 ret 52endfunc cortex_a57_disable_smp 53 54 /* --------------------------------------------- 55 * Disable debug interfaces 56 * --------------------------------------------- 57 */ 58func cortex_a57_disable_ext_debug 59 mov x0, #1 60 msr osdlr_el1, x0 61 isb 62#if ERRATA_A57_817169 63 /* 64 * Invalidate any TLB address 65 */ 66 mov x0, #0 67 tlbi vae3, x0 68#endif 69 dsb sy 70 ret 71endfunc cortex_a57_disable_ext_debug 72 73 /* -------------------------------------------------- 74 * Errata Workaround for Cortex A57 Errata #806969. 75 * This applies only to revision r0p0 of Cortex A57. 76 * Inputs: 77 * x0: variant[4:7] and revision[0:3] of current cpu. 78 * Shall clobber: x0-x17 79 * -------------------------------------------------- 80 */ 81func errata_a57_806969_wa 82 /* 83 * Compare x0 against revision r0p0 84 */ 85 mov x17, x30 86 bl check_errata_806969 87 cbz x0, 1f 88 mrs x1, CORTEX_A57_CPUACTLR_EL1 89 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA 90 msr CORTEX_A57_CPUACTLR_EL1, x1 911: 92 ret x17 93endfunc errata_a57_806969_wa 94 95func check_errata_806969 96 mov x1, #0x00 97 b cpu_rev_var_ls 98endfunc check_errata_806969 99 100 /* --------------------------------------------------- 101 * Errata Workaround for Cortex A57 Errata #813419. 102 * This applies only to revision r0p0 of Cortex A57. 103 * --------------------------------------------------- 104 */ 105func check_errata_813419 106 /* 107 * Even though this is only needed for revision r0p0, it 108 * is always applied due to limitations of the current 109 * errata framework. 110 */ 111 mov x0, #ERRATA_APPLIES 112 ret 113endfunc check_errata_813419 114 115 /* --------------------------------------------------- 116 * Errata Workaround for Cortex A57 Errata #813420. 117 * This applies only to revision r0p0 of Cortex A57. 118 * Inputs: 119 * x0: variant[4:7] and revision[0:3] of current cpu. 120 * Shall clobber: x0-x17 121 * --------------------------------------------------- 122 */ 123func errata_a57_813420_wa 124 /* 125 * Compare x0 against revision r0p0 126 */ 127 mov x17, x30 128 bl check_errata_813420 129 cbz x0, 1f 130 mrs x1, CORTEX_A57_CPUACTLR_EL1 131 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI 132 msr CORTEX_A57_CPUACTLR_EL1, x1 1331: 134 ret x17 135endfunc errata_a57_813420_wa 136 137func check_errata_813420 138 mov x1, #0x00 139 b cpu_rev_var_ls 140endfunc check_errata_813420 141 142 /* --------------------------------------------------- 143 * Errata Workaround for Cortex A57 Errata #814670. 144 * This applies only to revision r0p0 of Cortex A57. 145 * Inputs: 146 * x0: variant[4:7] and revision[0:3] of current cpu. 147 * Shall clobber: x0-x17 148 * --------------------------------------------------- 149 */ 150func errata_a57_814670_wa 151 /* 152 * Compare x0 against revision r0p0 153 */ 154 mov x17, x30 155 bl check_errata_814670 156 cbz x0, 1f 157 mrs x1, CORTEX_A57_CPUACTLR_EL1 158 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_DMB_NULLIFICATION 159 msr CORTEX_A57_CPUACTLR_EL1, x1 160 isb 1611: 162 ret x17 163endfunc errata_a57_814670_wa 164 165func check_errata_814670 166 mov x1, #0x00 167 b cpu_rev_var_ls 168endfunc check_errata_814670 169 170 /* ---------------------------------------------------- 171 * Errata Workaround for Cortex A57 Errata #817169. 172 * This applies only to revision <= r0p1 of Cortex A57. 173 * ---------------------------------------------------- 174 */ 175func check_errata_817169 176 /* 177 * Even though this is only needed for revision <= r0p1, it 178 * is always applied because of the low cost of the workaround. 179 */ 180 mov x0, #ERRATA_APPLIES 181 ret 182endfunc check_errata_817169 183 184 /* -------------------------------------------------------------------- 185 * Disable the over-read from the LDNP instruction. 186 * 187 * This applies to all revisions <= r1p2. The performance degradation 188 * observed with LDNP/STNP has been fixed on r1p3 and onwards. 189 * 190 * Inputs: 191 * x0: variant[4:7] and revision[0:3] of current cpu. 192 * Shall clobber: x0-x17 193 * --------------------------------------------------------------------- 194 */ 195func a57_disable_ldnp_overread 196 /* 197 * Compare x0 against revision r1p2 198 */ 199 mov x17, x30 200 bl check_errata_disable_ldnp_overread 201 cbz x0, 1f 202 mrs x1, CORTEX_A57_CPUACTLR_EL1 203 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD 204 msr CORTEX_A57_CPUACTLR_EL1, x1 2051: 206 ret x17 207endfunc a57_disable_ldnp_overread 208 209func check_errata_disable_ldnp_overread 210 mov x1, #0x12 211 b cpu_rev_var_ls 212endfunc check_errata_disable_ldnp_overread 213 214 /* --------------------------------------------------- 215 * Errata Workaround for Cortex A57 Errata #826974. 216 * This applies only to revision <= r1p1 of Cortex A57. 217 * Inputs: 218 * x0: variant[4:7] and revision[0:3] of current cpu. 219 * Shall clobber: x0-x17 220 * --------------------------------------------------- 221 */ 222func errata_a57_826974_wa 223 /* 224 * Compare x0 against revision r1p1 225 */ 226 mov x17, x30 227 bl check_errata_826974 228 cbz x0, 1f 229 mrs x1, CORTEX_A57_CPUACTLR_EL1 230 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB 231 msr CORTEX_A57_CPUACTLR_EL1, x1 2321: 233 ret x17 234endfunc errata_a57_826974_wa 235 236func check_errata_826974 237 mov x1, #0x11 238 b cpu_rev_var_ls 239endfunc check_errata_826974 240 241 /* --------------------------------------------------- 242 * Errata Workaround for Cortex A57 Errata #826977. 243 * This applies only to revision <= r1p1 of Cortex A57. 244 * Inputs: 245 * x0: variant[4:7] and revision[0:3] of current cpu. 246 * Shall clobber: x0-x17 247 * --------------------------------------------------- 248 */ 249func errata_a57_826977_wa 250 /* 251 * Compare x0 against revision r1p1 252 */ 253 mov x17, x30 254 bl check_errata_826977 255 cbz x0, 1f 256 mrs x1, CORTEX_A57_CPUACTLR_EL1 257 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE 258 msr CORTEX_A57_CPUACTLR_EL1, x1 2591: 260 ret x17 261endfunc errata_a57_826977_wa 262 263func check_errata_826977 264 mov x1, #0x11 265 b cpu_rev_var_ls 266endfunc check_errata_826977 267 268 /* --------------------------------------------------- 269 * Errata Workaround for Cortex A57 Errata #828024. 270 * This applies only to revision <= r1p1 of Cortex A57. 271 * Inputs: 272 * x0: variant[4:7] and revision[0:3] of current cpu. 273 * Shall clobber: x0-x17 274 * --------------------------------------------------- 275 */ 276func errata_a57_828024_wa 277 /* 278 * Compare x0 against revision r1p1 279 */ 280 mov x17, x30 281 bl check_errata_828024 282 cbz x0, 1f 283 mrs x1, CORTEX_A57_CPUACTLR_EL1 284 /* 285 * Setting the relevant bits in CPUACTLR_EL1 has to be done in 2 286 * instructions here because the resulting bitmask doesn't fit in a 287 * 16-bit value so it cannot be encoded in a single instruction. 288 */ 289 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA 290 orr x1, x1, #(CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING | \ 291 CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING) 292 msr CORTEX_A57_CPUACTLR_EL1, x1 2931: 294 ret x17 295endfunc errata_a57_828024_wa 296 297func check_errata_828024 298 mov x1, #0x11 299 b cpu_rev_var_ls 300endfunc check_errata_828024 301 302 /* --------------------------------------------------- 303 * Errata Workaround for Cortex A57 Errata #829520. 304 * This applies only to revision <= r1p2 of Cortex A57. 305 * Inputs: 306 * x0: variant[4:7] and revision[0:3] of current cpu. 307 * Shall clobber: x0-x17 308 * --------------------------------------------------- 309 */ 310func errata_a57_829520_wa 311 /* 312 * Compare x0 against revision r1p2 313 */ 314 mov x17, x30 315 bl check_errata_829520 316 cbz x0, 1f 317 mrs x1, CORTEX_A57_CPUACTLR_EL1 318 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR 319 msr CORTEX_A57_CPUACTLR_EL1, x1 3201: 321 ret x17 322endfunc errata_a57_829520_wa 323 324func check_errata_829520 325 mov x1, #0x12 326 b cpu_rev_var_ls 327endfunc check_errata_829520 328 329 /* --------------------------------------------------- 330 * Errata Workaround for Cortex A57 Errata #833471. 331 * This applies only to revision <= r1p2 of Cortex A57. 332 * Inputs: 333 * x0: variant[4:7] and revision[0:3] of current cpu. 334 * Shall clobber: x0-x17 335 * --------------------------------------------------- 336 */ 337func errata_a57_833471_wa 338 /* 339 * Compare x0 against revision r1p2 340 */ 341 mov x17, x30 342 bl check_errata_833471 343 cbz x0, 1f 344 mrs x1, CORTEX_A57_CPUACTLR_EL1 345 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH 346 msr CORTEX_A57_CPUACTLR_EL1, x1 3471: 348 ret x17 349endfunc errata_a57_833471_wa 350 351func check_errata_833471 352 mov x1, #0x12 353 b cpu_rev_var_ls 354endfunc check_errata_833471 355 356 /* -------------------------------------------------- 357 * Errata Workaround for Cortex A57 Errata #859972. 358 * This applies only to revision <= r1p3 of Cortex A57. 359 * Inputs: 360 * x0: variant[4:7] and revision[0:3] of current cpu. 361 * Shall clobber: 362 * -------------------------------------------------- 363 */ 364func errata_a57_859972_wa 365 mov x17, x30 366 bl check_errata_859972 367 cbz x0, 1f 368 mrs x1, CORTEX_A57_CPUACTLR_EL1 369 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH 370 msr CORTEX_A57_CPUACTLR_EL1, x1 3711: 372 ret x17 373endfunc errata_a57_859972_wa 374 375func check_errata_859972 376 mov x1, #0x13 377 b cpu_rev_var_ls 378endfunc check_errata_859972 379 380func check_errata_cve_2017_5715 381#if WORKAROUND_CVE_2017_5715 382 mov x0, #ERRATA_APPLIES 383#else 384 mov x0, #ERRATA_MISSING 385#endif 386 ret 387endfunc check_errata_cve_2017_5715 388 389func check_errata_cve_2018_3639 390#if WORKAROUND_CVE_2018_3639 391 mov x0, #ERRATA_APPLIES 392#else 393 mov x0, #ERRATA_MISSING 394#endif 395 ret 396endfunc check_errata_cve_2018_3639 397 398 /* ------------------------------------------------- 399 * The CPU Ops reset function for Cortex-A57. 400 * Shall clobber: x0-x19 401 * ------------------------------------------------- 402 */ 403func cortex_a57_reset_func 404 mov x19, x30 405 bl cpu_get_rev_var 406 mov x18, x0 407 408#if ERRATA_A57_806969 409 mov x0, x18 410 bl errata_a57_806969_wa 411#endif 412 413#if ERRATA_A57_813420 414 mov x0, x18 415 bl errata_a57_813420_wa 416#endif 417 418#if ERRATA_A57_814670 419 mov x0, x18 420 bl errata_a57_814670_wa 421#endif 422 423#if A57_DISABLE_NON_TEMPORAL_HINT 424 mov x0, x18 425 bl a57_disable_ldnp_overread 426#endif 427 428#if ERRATA_A57_826974 429 mov x0, x18 430 bl errata_a57_826974_wa 431#endif 432 433#if ERRATA_A57_826977 434 mov x0, x18 435 bl errata_a57_826977_wa 436#endif 437 438#if ERRATA_A57_828024 439 mov x0, x18 440 bl errata_a57_828024_wa 441#endif 442 443#if ERRATA_A57_829520 444 mov x0, x18 445 bl errata_a57_829520_wa 446#endif 447 448#if ERRATA_A57_833471 449 mov x0, x18 450 bl errata_a57_833471_wa 451#endif 452 453#if ERRATA_A57_859972 454 mov x0, x18 455 bl errata_a57_859972_wa 456#endif 457 458#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 459 adr x0, wa_cve_2017_5715_mmu_vbar 460 msr vbar_el3, x0 461 /* isb will be performed before returning from this function */ 462#endif 463 464#if WORKAROUND_CVE_2018_3639 465 mrs x0, CORTEX_A57_CPUACTLR_EL1 466 orr x0, x0, #CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_STORE 467 msr CORTEX_A57_CPUACTLR_EL1, x0 468 isb 469 dsb sy 470#endif 471 472 /* --------------------------------------------- 473 * Enable the SMP bit. 474 * --------------------------------------------- 475 */ 476 mrs x0, CORTEX_A57_ECTLR_EL1 477 orr x0, x0, #CORTEX_A57_ECTLR_SMP_BIT 478 msr CORTEX_A57_ECTLR_EL1, x0 479 isb 480 ret x19 481endfunc cortex_a57_reset_func 482 483 /* ---------------------------------------------------- 484 * The CPU Ops core power down function for Cortex-A57. 485 * ---------------------------------------------------- 486 */ 487func cortex_a57_core_pwr_dwn 488 mov x18, x30 489 490 /* --------------------------------------------- 491 * Turn off caches. 492 * --------------------------------------------- 493 */ 494 bl cortex_a57_disable_dcache 495 496 /* --------------------------------------------- 497 * Disable the L2 prefetches. 498 * --------------------------------------------- 499 */ 500 bl cortex_a57_disable_l2_prefetch 501 502 /* --------------------------------------------- 503 * Flush L1 caches. 504 * --------------------------------------------- 505 */ 506 mov x0, #DCCISW 507 bl dcsw_op_level1 508 509 /* --------------------------------------------- 510 * Come out of intra cluster coherency 511 * --------------------------------------------- 512 */ 513 bl cortex_a57_disable_smp 514 515 /* --------------------------------------------- 516 * Force the debug interfaces to be quiescent 517 * --------------------------------------------- 518 */ 519 mov x30, x18 520 b cortex_a57_disable_ext_debug 521endfunc cortex_a57_core_pwr_dwn 522 523 /* ------------------------------------------------------- 524 * The CPU Ops cluster power down function for Cortex-A57. 525 * ------------------------------------------------------- 526 */ 527func cortex_a57_cluster_pwr_dwn 528 mov x18, x30 529 530 /* --------------------------------------------- 531 * Turn off caches. 532 * --------------------------------------------- 533 */ 534 bl cortex_a57_disable_dcache 535 536 /* --------------------------------------------- 537 * Disable the L2 prefetches. 538 * --------------------------------------------- 539 */ 540 bl cortex_a57_disable_l2_prefetch 541 542#if !SKIP_A57_L1_FLUSH_PWR_DWN 543 /* ------------------------------------------------- 544 * Flush the L1 caches. 545 * ------------------------------------------------- 546 */ 547 mov x0, #DCCISW 548 bl dcsw_op_level1 549#endif 550 /* --------------------------------------------- 551 * Disable the optional ACP. 552 * --------------------------------------------- 553 */ 554 bl plat_disable_acp 555 556 /* ------------------------------------------------- 557 * Flush the L2 caches. 558 * ------------------------------------------------- 559 */ 560 mov x0, #DCCISW 561 bl dcsw_op_level2 562 563 /* --------------------------------------------- 564 * Come out of intra cluster coherency 565 * --------------------------------------------- 566 */ 567 bl cortex_a57_disable_smp 568 569 /* --------------------------------------------- 570 * Force the debug interfaces to be quiescent 571 * --------------------------------------------- 572 */ 573 mov x30, x18 574 b cortex_a57_disable_ext_debug 575endfunc cortex_a57_cluster_pwr_dwn 576 577#if REPORT_ERRATA 578/* 579 * Errata printing function for Cortex A57. Must follow AAPCS. 580 */ 581func cortex_a57_errata_report 582 stp x8, x30, [sp, #-16]! 583 584 bl cpu_get_rev_var 585 mov x8, x0 586 587 /* 588 * Report all errata. The revision-variant information is passed to 589 * checking functions of each errata. 590 */ 591 report_errata ERRATA_A57_806969, cortex_a57, 806969 592 report_errata ERRATA_A57_813419, cortex_a57, 813419 593 report_errata ERRATA_A57_813420, cortex_a57, 813420 594 report_errata ERRATA_A57_814670, cortex_a57, 814670 595 report_errata ERRATA_A57_817169, cortex_a57, 817169 596 report_errata A57_DISABLE_NON_TEMPORAL_HINT, cortex_a57, \ 597 disable_ldnp_overread 598 report_errata ERRATA_A57_826974, cortex_a57, 826974 599 report_errata ERRATA_A57_826977, cortex_a57, 826977 600 report_errata ERRATA_A57_828024, cortex_a57, 828024 601 report_errata ERRATA_A57_829520, cortex_a57, 829520 602 report_errata ERRATA_A57_833471, cortex_a57, 833471 603 report_errata ERRATA_A57_859972, cortex_a57, 859972 604 report_errata WORKAROUND_CVE_2017_5715, cortex_a57, cve_2017_5715 605 report_errata WORKAROUND_CVE_2018_3639, cortex_a57, cve_2018_3639 606 607 ldp x8, x30, [sp], #16 608 ret 609endfunc cortex_a57_errata_report 610#endif 611 612 /* --------------------------------------------- 613 * This function provides cortex_a57 specific 614 * register information for crash reporting. 615 * It needs to return with x6 pointing to 616 * a list of register names in ascii and 617 * x8 - x15 having values of registers to be 618 * reported. 619 * --------------------------------------------- 620 */ 621.section .rodata.cortex_a57_regs, "aS" 622cortex_a57_regs: /* The ascii list of register names to be reported */ 623 .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" 624 625func cortex_a57_cpu_reg_dump 626 adr x6, cortex_a57_regs 627 mrs x8, CORTEX_A57_ECTLR_EL1 628 mrs x9, CORTEX_A57_MERRSR_EL1 629 mrs x10, CORTEX_A57_L2MERRSR_EL1 630 ret 631endfunc cortex_a57_cpu_reg_dump 632 633declare_cpu_ops_wa cortex_a57, CORTEX_A57_MIDR, \ 634 cortex_a57_reset_func, \ 635 check_errata_cve_2017_5715, \ 636 CPU_NO_EXTRA2_FUNC, \ 637 cortex_a57_core_pwr_dwn, \ 638 cortex_a57_cluster_pwr_dwn 639