1/* 2 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30#include <arch.h> 31#include <asm_macros.S> 32#include <assert_macros.S> 33#include <cortex_a57.h> 34#include <cpu_macros.S> 35#include <plat_macros.S> 36 37 /* --------------------------------------------- 38 * Disable L1 data cache and unified L2 cache 39 * --------------------------------------------- 40 */ 41func cortex_a57_disable_dcache 42 mrs x1, sctlr_el3 43 bic x1, x1, #SCTLR_C_BIT 44 msr sctlr_el3, x1 45 isb 46 ret 47 48 /* --------------------------------------------- 49 * Disable all types of L2 prefetches. 50 * --------------------------------------------- 51 */ 52func cortex_a57_disable_l2_prefetch 53 mrs x0, CPUECTLR_EL1 54 orr x0, x0, #CPUECTLR_DIS_TWD_ACC_PFTCH_BIT 55 mov x1, #CPUECTLR_L2_IPFTCH_DIST_MASK 56 orr x1, x1, #CPUECTLR_L2_DPFTCH_DIST_MASK 57 bic x0, x0, x1 58 msr CPUECTLR_EL1, x0 59 isb 60 dsb ish 61 ret 62 63 /* --------------------------------------------- 64 * Disable intra-cluster coherency 65 * --------------------------------------------- 66 */ 67func cortex_a57_disable_smp 68 mrs x0, CPUECTLR_EL1 69 bic x0, x0, #CPUECTLR_SMP_BIT 70 msr CPUECTLR_EL1, x0 71 ret 72 73 /* --------------------------------------------- 74 * Disable debug interfaces 75 * --------------------------------------------- 76 */ 77func cortex_a57_disable_ext_debug 78 mov x0, #1 79 msr osdlr_el1, x0 80 isb 81 dsb sy 82 ret 83 84 /* -------------------------------------------------- 85 * Errata Workaround for Cortex A57 Errata #806969. 86 * This applies only to revision r0p0 of Cortex A57. 87 * Inputs: 88 * x0: variant[4:7] and revision[0:3] of current cpu. 89 * -------------------------------------------------- 90 */ 91func errata_a57_806969_wa 92 /* 93 * Compare x0 against revision r0p0 94 */ 95 cbz x0, apply_806969 96#if DEBUG 97 b print_revision_warning 98#else 99 ret 100#endif 101apply_806969: 102 mrs x1, CPUACTLR_EL1 103 orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA 104 msr CPUACTLR_EL1, x1 105 ret 106 107 108 /* --------------------------------------------------- 109 * Errata Workaround for Cortex A57 Errata #813420. 110 * This applies only to revision r0p0 of Cortex A57. 111 * Inputs: 112 * x0: variant[4:7] and revision[0:3] of current cpu. 113 * --------------------------------------------------- 114 */ 115func errata_a57_813420_wa 116 /* 117 * Compare x0 against revision r0p0 118 */ 119 cbz x0, apply_813420 120#if DEBUG 121 b print_revision_warning 122#else 123 ret 124#endif 125apply_813420: 126 mrs x1, CPUACTLR_EL1 127 orr x1, x1, #CPUACTLR_DCC_AS_DCCI 128 msr CPUACTLR_EL1, x1 129 ret 130 131 /* ------------------------------------------------- 132 * The CPU Ops reset function for Cortex-A57. 133 * ------------------------------------------------- 134 */ 135func cortex_a57_reset_func 136 mov x19, x30 137 mrs x0, midr_el1 138 139 /* 140 * Extract the variant[20:23] and revision[0:3] from x0 141 * and pack it in x20[0:7] as variant[4:7] and revision[0:3]. 142 * First extract x0[16:23] to x20[0:7] and zero fill the rest. 143 * Then extract x0[0:3] into x20[0:3] retaining other bits. 144 */ 145 ubfx x20, x0, #(MIDR_VAR_SHIFT - MIDR_REV_BITS), #(MIDR_REV_BITS + MIDR_VAR_BITS) 146 bfxil x20, x0, #MIDR_REV_SHIFT, #MIDR_REV_BITS 147 148#if ERRATA_A57_806969 149 mov x0, x20 150 bl errata_a57_806969_wa 151#endif 152 153#if ERRATA_A57_813420 154 mov x0, x20 155 bl errata_a57_813420_wa 156#endif 157 /* --------------------------------------------- 158 * As a bare minimum enable the SMP bit. 159 * --------------------------------------------- 160 */ 161 mrs x0, CPUECTLR_EL1 162 orr x0, x0, #CPUECTLR_SMP_BIT 163 msr CPUECTLR_EL1, x0 164 isb 165 ret x19 166 167 /* ---------------------------------------------------- 168 * The CPU Ops core power down function for Cortex-A57. 169 * ---------------------------------------------------- 170 */ 171func cortex_a57_core_pwr_dwn 172 mov x18, x30 173 174 /* --------------------------------------------- 175 * Turn off caches. 176 * --------------------------------------------- 177 */ 178 bl cortex_a57_disable_dcache 179 180 /* --------------------------------------------- 181 * Disable the L2 prefetches. 182 * --------------------------------------------- 183 */ 184 bl cortex_a57_disable_l2_prefetch 185 186 /* --------------------------------------------- 187 * Flush L1 caches. 188 * --------------------------------------------- 189 */ 190 mov x0, #DCCISW 191 bl dcsw_op_level1 192 193 /* --------------------------------------------- 194 * Come out of intra cluster coherency 195 * --------------------------------------------- 196 */ 197 bl cortex_a57_disable_smp 198 199 /* --------------------------------------------- 200 * Force the debug interfaces to be quiescent 201 * --------------------------------------------- 202 */ 203 mov x30, x18 204 b cortex_a57_disable_ext_debug 205 206 /* ------------------------------------------------------- 207 * The CPU Ops cluster power down function for Cortex-A57. 208 * ------------------------------------------------------- 209 */ 210func cortex_a57_cluster_pwr_dwn 211 mov x18, x30 212 213 /* --------------------------------------------- 214 * Turn off caches. 215 * --------------------------------------------- 216 */ 217 bl cortex_a57_disable_dcache 218 219 /* --------------------------------------------- 220 * Disable the L2 prefetches. 221 * --------------------------------------------- 222 */ 223 bl cortex_a57_disable_l2_prefetch 224 225#if !SKIP_A57_L1_FLUSH_PWR_DWN 226 /* ------------------------------------------------- 227 * Flush the L1 caches. 228 * ------------------------------------------------- 229 */ 230 mov x0, #DCCISW 231 bl dcsw_op_level1 232#endif 233 /* --------------------------------------------- 234 * Disable the optional ACP. 235 * --------------------------------------------- 236 */ 237 bl plat_disable_acp 238 239 /* ------------------------------------------------- 240 * Flush the L2 caches. 241 * ------------------------------------------------- 242 */ 243 mov x0, #DCCISW 244 bl dcsw_op_level2 245 246 /* --------------------------------------------- 247 * Come out of intra cluster coherency 248 * --------------------------------------------- 249 */ 250 bl cortex_a57_disable_smp 251 252 /* --------------------------------------------- 253 * Force the debug interfaces to be quiescent 254 * --------------------------------------------- 255 */ 256 mov x30, x18 257 b cortex_a57_disable_ext_debug 258 259 /* --------------------------------------------- 260 * This function provides cortex_a57 specific 261 * register information for crash reporting. 262 * It needs to return with x6 pointing to 263 * a list of register names in ascii and 264 * x8 - x15 having values of registers to be 265 * reported. 266 * --------------------------------------------- 267 */ 268.section .rodata.cortex_a57_regs, "aS" 269cortex_a57_regs: /* The ascii list of register names to be reported */ 270 .asciz "cpuectlr_el1", "" 271 272func cortex_a57_cpu_reg_dump 273 adr x6, cortex_a57_regs 274 mrs x8, CPUECTLR_EL1 275 ret 276 277 278declare_cpu_ops cortex_a57, CORTEX_A57_MIDR 279