1/* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a55.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14 /* -------------------------------------------------- 15 * Errata Workaround for Cortex A55 Errata #768277. 16 * This applies only to revision r0p0 of Cortex A55. 17 * Inputs: 18 * x0: variant[4:7] and revision[0:3] of current cpu. 19 * Shall clobber: x0-x17 20 * -------------------------------------------------- 21 */ 22func errata_a55_768277_wa 23 /* 24 * Compare x0 against revision r0p0 25 */ 26 mov x17, x30 27 bl check_errata_768277 28 cbz x0, 1f 29 mrs x1, CORTEX_A55_CPUACTLR_EL1 30 orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE 31 msr CORTEX_A55_CPUACTLR_EL1, x1 32 isb 331: 34 ret x17 35endfunc errata_a55_768277_wa 36 37func check_errata_768277 38 mov x1, #0x00 39 b cpu_rev_var_ls 40endfunc check_errata_768277 41 42 /* ------------------------------------------------------------------ 43 * Errata Workaround for Cortex A55 Errata #778703. 44 * This applies only to revision r0p0 of Cortex A55 where L2 cache is 45 * not configured. 46 * Inputs: 47 * x0: variant[4:7] and revision[0:3] of current cpu. 48 * Shall clobber: x0-x17 49 * ------------------------------------------------------------------ 50 */ 51func errata_a55_778703_wa 52 /* 53 * Compare x0 against revision r0p0 and check that no private L2 cache 54 * is configured 55 */ 56 mov x17, x30 57 bl check_errata_778703 58 cbz x0, 1f 59 mrs x1, CORTEX_A55_CPUECTLR_EL1 60 orr x1, x1, #CORTEX_A55_CPUECTLR_EL1_L1WSCTL 61 msr CORTEX_A55_CPUECTLR_EL1, x1 62 mrs x1, CORTEX_A55_CPUACTLR_EL1 63 orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING 64 msr CORTEX_A55_CPUACTLR_EL1, x1 65 isb 661: 67 ret x17 68endfunc errata_a55_778703_wa 69 70func check_errata_778703 71 mov x16, x30 72 mov x1, #0x00 73 bl cpu_rev_var_ls 74 /* 75 * Check that no private L2 cache is configured 76 */ 77 mrs x1, CORTEX_A55_CLIDR_EL1 78 and x1, x1, CORTEX_A55_CLIDR_EL1_CTYPE3 79 cmp x1, #0 80 mov x2, #ERRATA_NOT_APPLIES 81 csel x0, x0, x2, eq 82 ret x16 83endfunc check_errata_778703 84 85 /* -------------------------------------------------- 86 * Errata Workaround for Cortex A55 Errata #798797. 87 * This applies only to revision r0p0 of Cortex A55. 88 * Inputs: 89 * x0: variant[4:7] and revision[0:3] of current cpu. 90 * Shall clobber: x0-x17 91 * -------------------------------------------------- 92 */ 93func errata_a55_798797_wa 94 /* 95 * Compare x0 against revision r0p0 96 */ 97 mov x17, x30 98 bl check_errata_798797 99 cbz x0, 1f 100 mrs x1, CORTEX_A55_CPUACTLR_EL1 101 orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS 102 msr CORTEX_A55_CPUACTLR_EL1, x1 103 isb 1041: 105 ret x17 106endfunc errata_a55_798797_wa 107 108func check_errata_798797 109 mov x1, #0x00 110 b cpu_rev_var_ls 111endfunc check_errata_798797 112 113 /* -------------------------------------------------------------------- 114 * Errata Workaround for Cortex A55 Errata #846532. 115 * This applies only to revisions <= r0p1 of Cortex A55. 116 * Disabling dual-issue has a small impact on performance. Disabling a 117 * power optimization feature is an alternate workaround with no impact 118 * on performance but with an increase in power consumption (see errata 119 * notice). 120 * Inputs: 121 * x0: variant[4:7] and revision[0:3] of current cpu. 122 * Shall clobber: x0-x17 123 * -------------------------------------------------------------------- 124 */ 125func errata_a55_846532_wa 126 /* 127 * Compare x0 against revision r0p1 128 */ 129 mov x17, x30 130 bl check_errata_846532 131 cbz x0, 1f 132 mrs x1, CORTEX_A55_CPUACTLR_EL1 133 orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE 134 msr CORTEX_A55_CPUACTLR_EL1, x1 135 isb 1361: 137 ret x17 138endfunc errata_a55_846532_wa 139 140func check_errata_846532 141 mov x1, #0x01 142 b cpu_rev_var_ls 143endfunc check_errata_846532 144 145 /* ----------------------------------------------------- 146 * Errata Workaround for Cortex A55 Errata #903758. 147 * This applies only to revisions <= r0p1 of Cortex A55. 148 * Inputs: 149 * x0: variant[4:7] and revision[0:3] of current cpu. 150 * Shall clobber: x0-x17 151 * ----------------------------------------------------- 152 */ 153func errata_a55_903758_wa 154 /* 155 * Compare x0 against revision r0p1 156 */ 157 mov x17, x30 158 bl check_errata_903758 159 cbz x0, 1f 160 mrs x1, CORTEX_A55_CPUACTLR_EL1 161 orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS 162 msr CORTEX_A55_CPUACTLR_EL1, x1 163 isb 1641: 165 ret x17 166endfunc errata_a55_903758_wa 167 168func check_errata_903758 169 mov x1, #0x01 170 b cpu_rev_var_ls 171endfunc check_errata_903758 172 173func cortex_a55_reset_func 174 mov x19, x30 175 176#if ERRATA_DSU_798953 177 bl errata_dsu_798953_wa 178#endif 179 180#if ERRATA_DSU_936184 181 bl errata_dsu_936184_wa 182#endif 183 184 bl cpu_get_rev_var 185 mov x18, x0 186 187#if ERRATA_A55_768277 188 mov x0, x18 189 bl errata_a55_768277_wa 190#endif 191 192#if ERRATA_A55_778703 193 mov x0, x18 194 bl errata_a55_778703_wa 195#endif 196 197#if ERRATA_A55_798797 198 mov x0, x18 199 bl errata_a55_798797_wa 200#endif 201 202#if ERRATA_A55_846532 203 mov x0, x18 204 bl errata_a55_846532_wa 205#endif 206 207#if ERRATA_A55_903758 208 mov x0, x18 209 bl errata_a55_903758_wa 210#endif 211 212 ret x19 213endfunc cortex_a55_reset_func 214 215 /* --------------------------------------------- 216 * HW will do the cache maintenance while powering down 217 * --------------------------------------------- 218 */ 219func cortex_a55_core_pwr_dwn 220 /* --------------------------------------------- 221 * Enable CPU power down bit in power control register 222 * --------------------------------------------- 223 */ 224 mrs x0, CORTEX_A55_CPUPWRCTLR_EL1 225 orr x0, x0, #CORTEX_A55_CORE_PWRDN_EN_MASK 226 msr CORTEX_A55_CPUPWRCTLR_EL1, x0 227 isb 228 ret 229endfunc cortex_a55_core_pwr_dwn 230 231#if REPORT_ERRATA 232/* 233 * Errata printing function for Cortex A55. Must follow AAPCS & can use stack. 234 */ 235func cortex_a55_errata_report 236 stp x8, x30, [sp, #-16]! 237 bl cpu_get_rev_var 238 mov x8, x0 239 240 /* 241 * Report all errata. The revision variant information is at x8, where 242 * "report_errata" is expecting it and it doesn't corrupt it. 243 */ 244 report_errata ERRATA_DSU_798953, cortex_a55, dsu_798953 245 report_errata ERRATA_DSU_936184, cortex_a55, dsu_936184 246 report_errata ERRATA_A55_768277, cortex_a55, 768277 247 report_errata ERRATA_A55_778703, cortex_a55, 778703 248 report_errata ERRATA_A55_798797, cortex_a55, 798797 249 report_errata ERRATA_A55_846532, cortex_a55, 846532 250 report_errata ERRATA_A55_903758, cortex_a55, 903758 251 252 ldp x8, x30, [sp], #16 253 ret 254endfunc cortex_a55_errata_report 255#endif 256 257 /* --------------------------------------------- 258 * This function provides cortex_a55 specific 259 * register information for crash reporting. 260 * It needs to return with x6 pointing to 261 * a list of register names in ascii and 262 * x8 - x15 having values of registers to be 263 * reported. 264 * --------------------------------------------- 265 */ 266.section .rodata.cortex_a55_regs, "aS" 267cortex_a55_regs: /* The ascii list of register names to be reported */ 268 .asciz "cpuectlr_el1", "" 269 270func cortex_a55_cpu_reg_dump 271 adr x6, cortex_a55_regs 272 mrs x8, CORTEX_A55_CPUECTLR_EL1 273 ret 274endfunc cortex_a55_cpu_reg_dump 275 276declare_cpu_ops cortex_a55, CORTEX_A55_MIDR, \ 277 cortex_a55_reset_func, \ 278 cortex_a55_core_pwr_dwn 279