1/* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a55.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14func cortex_a55_reset_func 15 mov x19, x30 16#if ERRATA_DSU_936184 17 bl errata_dsu_936184_wa 18#endif 19 ret x19 20endfunc cortex_a55_reset_func 21 22 /* --------------------------------------------- 23 * HW will do the cache maintenance while powering down 24 * --------------------------------------------- 25 */ 26func cortex_a55_core_pwr_dwn 27 /* --------------------------------------------- 28 * Enable CPU power down bit in power control register 29 * --------------------------------------------- 30 */ 31 mrs x0, CORTEX_A55_CPUPWRCTLR_EL1 32 orr x0, x0, #CORTEX_A55_CORE_PWRDN_EN_MASK 33 msr CORTEX_A55_CPUPWRCTLR_EL1, x0 34 isb 35 ret 36endfunc cortex_a55_core_pwr_dwn 37 38#if REPORT_ERRATA 39/* 40 * Errata printing function for Cortex A55. Must follow AAPCS & can use stack. 41 */ 42func cortex_a55_errata_report 43 stp x8, x30, [sp, #-16]! 44 bl cpu_get_rev_var 45 mov x8, x0 46 47 /* 48 * Report all errata. The revision variant information is at x8, where 49 * "report_errata" is expecting it and it doesn't corrupt it. 50 */ 51 report_errata ERRATA_DSU_936184, cortex_a55, dsu_936184 52 53 ldp x8, x30, [sp], #16 54 ret 55endfunc cortex_a55_errata_report 56#endif 57 58 /* --------------------------------------------- 59 * This function provides cortex_a55 specific 60 * register information for crash reporting. 61 * It needs to return with x6 pointing to 62 * a list of register names in ascii and 63 * x8 - x15 having values of registers to be 64 * reported. 65 * --------------------------------------------- 66 */ 67.section .rodata.cortex_a55_regs, "aS" 68cortex_a55_regs: /* The ascii list of register names to be reported */ 69 .asciz "cpuectlr_el1", "" 70 71func cortex_a55_cpu_reg_dump 72 adr x6, cortex_a55_regs 73 mrs x8, CORTEX_A55_CPUECTLR_EL1 74 ret 75endfunc cortex_a55_cpu_reg_dump 76 77declare_cpu_ops cortex_a55, CORTEX_A55_MIDR, \ 78 cortex_a55_reset_func, \ 79 cortex_a55_core_pwr_dwn 80