1/* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <bl_common.h> 10#include <cortex_a55.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14 /* --------------------------------------------- 15 * HW will do the cache maintenance while powering down 16 * --------------------------------------------- 17 */ 18func cortex_a55_core_pwr_dwn 19 /* --------------------------------------------- 20 * Enable CPU power down bit in power control register 21 * --------------------------------------------- 22 */ 23 mrs x0, CORTEX_A55_CPUPWRCTLR_EL1 24 orr x0, x0, #CORTEX_A55_CORE_PWRDN_EN_MASK 25 msr CORTEX_A55_CPUPWRCTLR_EL1, x0 26 isb 27 ret 28endfunc cortex_a55_core_pwr_dwn 29 30 /* --------------------------------------------- 31 * This function provides cortex_a55 specific 32 * register information for crash reporting. 33 * It needs to return with x6 pointing to 34 * a list of register names in ascii and 35 * x8 - x15 having values of registers to be 36 * reported. 37 * --------------------------------------------- 38 */ 39.section .rodata.cortex_a55_regs, "aS" 40cortex_a55_regs: /* The ascii list of register names to be reported */ 41 .asciz "cpuectlr_el1", "" 42 43func cortex_a55_cpu_reg_dump 44 adr x6, cortex_a55_regs 45 mrs x8, CORTEX_A55_CPUECTLR_EL1 46 ret 47endfunc cortex_a55_cpu_reg_dump 48 49declare_cpu_ops cortex_a55, CORTEX_A55_MIDR, \ 50 CPU_NO_RESET_FUNC, \ 51 cortex_a55_core_pwr_dwn 52