1/* 2 * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a55.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-A55 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20 .globl cortex_a55_reset_func 21 .globl cortex_a55_core_pwr_dwn 22 23cpu_reset_prologue cortex_a55 24 25workaround_reset_start cortex_a55, ERRATUM(768277), ERRATA_A55_768277 26 sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE 27workaround_reset_end cortex_a55, ERRATUM(768277) 28 29check_erratum_ls cortex_a55, ERRATUM(768277), CPU_REV(0, 0) 30 31workaround_reset_start cortex_a55, ERRATUM(778703), ERRATA_A55_778703 32 sysreg_bit_set CORTEX_A55_CPUECTLR_EL1, CORTEX_A55_CPUECTLR_EL1_L1WSCTL 33 sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING 34workaround_reset_end cortex_a55, ERRATUM(778703) 35 36check_erratum_custom_start cortex_a55, ERRATUM(778703) 37 mov x16, x30 38 cpu_rev_var_ls CPU_REV(0, 0) 39 /* 40 * Check that no private L2 cache is configured 41 */ 42 mrs x1, CORTEX_A55_CLIDR_EL1 43 and x1, x1, CORTEX_A55_CLIDR_EL1_CTYPE3 44 cmp x1, #0 45 mov x2, #ERRATA_NOT_APPLIES 46 csel x0, x0, x2, eq 47 ret x16 48check_erratum_custom_end cortex_a55, ERRATUM(778703) 49 50workaround_reset_start cortex_a55, ERRATUM(798797), ERRATA_A55_798797 51 sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS 52workaround_reset_end cortex_a55, ERRATUM(798797) 53 54check_erratum_ls cortex_a55, ERRATUM(798797), CPU_REV(0, 0) 55 56workaround_reset_start cortex_a55, ERRATUM(798953), ERRATA_DSU_798953 57 errata_dsu_798953_wa_impl 58workaround_reset_end cortex_a55, ERRATUM(798953) 59 60check_erratum_custom_start cortex_a55, ERRATUM(798953) 61 check_errata_dsu_798953_impl 62 ret 63check_erratum_custom_end cortex_a55, ERRATUM(798953) 64 65workaround_reset_start cortex_a55, ERRATUM(846532), ERRATA_A55_846532 66 sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE 67workaround_reset_end cortex_a55, ERRATUM(846532) 68 69check_erratum_ls cortex_a55, ERRATUM(846532), CPU_REV(0, 1) 70 71workaround_reset_start cortex_a55, ERRATUM(903758), ERRATA_A55_903758 72 sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS 73workaround_reset_end cortex_a55, ERRATUM(903758) 74 75check_erratum_ls cortex_a55, ERRATUM(903758), CPU_REV(0, 1) 76 77workaround_reset_start cortex_a55, ERRATUM(936184), ERRATA_DSU_936184 78 errata_dsu_936184_wa_impl 79workaround_reset_end cortex_a55, ERRATUM(936184) 80 81check_erratum_custom_start cortex_a55, ERRATUM(936184) 82 check_errata_dsu_936184_impl 83 ret 84check_erratum_custom_end cortex_a55, ERRATUM(936184) 85 86workaround_reset_start cortex_a55, ERRATUM(1221012), ERRATA_A55_1221012 87 mov x0, #0x0020 88 movk x0, #0x0850, lsl #16 89 msr CPUPOR_EL3, x0 90 mov x0, #0x0000 91 movk x0, #0x1FF0, lsl #16 92 movk x0, #0x2, lsl #32 93 msr CPUPMR_EL3, x0 94 mov x0, #0x03fd 95 movk x0, #0x0110, lsl #16 96 msr CPUPCR_EL3, x0 97 mov x0, #0x1 98 msr CPUPSELR_EL3, x0 99 mov x0, #0x0040 100 movk x0, #0x08D0, lsl #16 101 msr CPUPOR_EL3, x0 102 mov x0, #0x0040 103 movk x0, #0x1FF0, lsl #16 104 movk x0, #0x2, lsl #32 105 msr CPUPMR_EL3, x0 106 mov x0, #0x03fd 107 movk x0, #0x0110, lsl #16 108 msr CPUPCR_EL3, x0 109workaround_reset_end cortex_a55, ERRATUM(1221012) 110 111check_erratum_ls cortex_a55, ERRATUM(1221012), CPU_REV(1, 0) 112 113check_erratum_chosen cortex_a55, ERRATUM(1530923), ERRATA_A55_1530923 114 115/* erratum has no workaround in the cpu. Generic code must take care */ 116add_erratum_entry cortex_a55, ERRATUM(1530923), ERRATA_A55_1530923 117 118cpu_reset_func_start cortex_a55 119cpu_reset_func_end cortex_a55 120 121 /* --------------------------------------------- 122 * HW will do the cache maintenance while powering down 123 * --------------------------------------------- 124 */ 125func cortex_a55_core_pwr_dwn 126 sysreg_bit_set CORTEX_A55_CPUPWRCTLR_EL1, CORTEX_A55_CORE_PWRDN_EN_MASK 127 isb 128 ret 129endfunc cortex_a55_core_pwr_dwn 130 131 /* --------------------------------------------- 132 * This function provides cortex_a55 specific 133 * register information for crash reporting. 134 * It needs to return with x6 pointing to 135 * a list of register names in ascii and 136 * x8 - x15 having values of registers to be 137 * reported. 138 * --------------------------------------------- 139 */ 140.section .rodata.cortex_a55_regs, "aS" 141cortex_a55_regs: /* The ascii list of register names to be reported */ 142 .asciz "cpuectlr_el1", "" 143 144func cortex_a55_cpu_reg_dump 145 adr x6, cortex_a55_regs 146 mrs x8, CORTEX_A55_CPUECTLR_EL1 147 ret 148endfunc cortex_a55_cpu_reg_dump 149 150declare_cpu_ops cortex_a55, CORTEX_A55_MIDR, \ 151 cortex_a55_reset_func, \ 152 cortex_a55_core_pwr_dwn 153