1/* 2 * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <common/bl_common.h> 9#include <common/debug.h> 10#include <cortex_a53.h> 11#include <cpu_macros.S> 12#include <lib/cpus/errata_report.h> 13#include <plat_macros.S> 14 15#if A53_DISABLE_NON_TEMPORAL_HINT 16#undef ERRATA_A53_836870 17#define ERRATA_A53_836870 1 18#endif 19 20 /* --------------------------------------------- 21 * Disable L1 data cache and unified L2 cache 22 * --------------------------------------------- 23 */ 24func cortex_a53_disable_dcache 25 mrs x1, sctlr_el3 26 bic x1, x1, #SCTLR_C_BIT 27 msr sctlr_el3, x1 28 isb 29 ret 30endfunc cortex_a53_disable_dcache 31 32 /* --------------------------------------------- 33 * Disable intra-cluster coherency 34 * --------------------------------------------- 35 */ 36func cortex_a53_disable_smp 37 mrs x0, CORTEX_A53_ECTLR_EL1 38 bic x0, x0, #CORTEX_A53_ECTLR_SMP_BIT 39 msr CORTEX_A53_ECTLR_EL1, x0 40 isb 41 dsb sy 42 ret 43endfunc cortex_a53_disable_smp 44 45 /* --------------------------------------------------- 46 * Errata Workaround for Cortex A53 Errata #819472. 47 * This applies only to revision <= r0p1 of Cortex A53. 48 * --------------------------------------------------- 49 */ 50func check_errata_819472 51 /* 52 * Even though this is only needed for revision <= r0p1, it 53 * is always applied due to limitations of the current 54 * errata framework. 55 */ 56 mov x0, #ERRATA_APPLIES 57 ret 58endfunc check_errata_819472 59 60 /* --------------------------------------------------- 61 * Errata Workaround for Cortex A53 Errata #824069. 62 * This applies only to revision <= r0p2 of Cortex A53. 63 * --------------------------------------------------- 64 */ 65func check_errata_824069 66 /* 67 * Even though this is only needed for revision <= r0p2, it 68 * is always applied due to limitations of the current 69 * errata framework. 70 */ 71 mov x0, #ERRATA_APPLIES 72 ret 73endfunc check_errata_824069 74 75 /* -------------------------------------------------- 76 * Errata Workaround for Cortex A53 Errata #826319. 77 * This applies only to revision <= r0p2 of Cortex A53. 78 * Inputs: 79 * x0: variant[4:7] and revision[0:3] of current cpu. 80 * Shall clobber: x0-x17 81 * -------------------------------------------------- 82 */ 83func errata_a53_826319_wa 84 /* 85 * Compare x0 against revision r0p2 86 */ 87 mov x17, x30 88 bl check_errata_826319 89 cbz x0, 1f 90 mrs x1, CORTEX_A53_L2ACTLR_EL1 91 bic x1, x1, #CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN 92 orr x1, x1, #CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH 93 msr CORTEX_A53_L2ACTLR_EL1, x1 941: 95 ret x17 96endfunc errata_a53_826319_wa 97 98func check_errata_826319 99 mov x1, #0x02 100 b cpu_rev_var_ls 101endfunc check_errata_826319 102 103 /* --------------------------------------------------- 104 * Errata Workaround for Cortex A53 Errata #827319. 105 * This applies only to revision <= r0p2 of Cortex A53. 106 * --------------------------------------------------- 107 */ 108func check_errata_827319 109 /* 110 * Even though this is only needed for revision <= r0p2, it 111 * is always applied due to limitations of the current 112 * errata framework. 113 */ 114 mov x0, #ERRATA_APPLIES 115 ret 116endfunc check_errata_827319 117 118 /* --------------------------------------------------------------------- 119 * Disable the cache non-temporal hint. 120 * 121 * This ignores the Transient allocation hint in the MAIR and treats 122 * allocations the same as non-transient allocation types. As a result, 123 * the LDNP and STNP instructions in AArch64 behave the same as the 124 * equivalent LDP and STP instructions. 125 * 126 * This is relevant only for revisions <= r0p3 of Cortex-A53. 127 * From r0p4 and onwards, the bit to disable the hint is enabled by 128 * default at reset. 129 * 130 * Inputs: 131 * x0: variant[4:7] and revision[0:3] of current cpu. 132 * Shall clobber: x0-x17 133 * --------------------------------------------------------------------- 134 */ 135func a53_disable_non_temporal_hint 136 /* 137 * Compare x0 against revision r0p3 138 */ 139 mov x17, x30 140 bl check_errata_disable_non_temporal_hint 141 cbz x0, 1f 142 mrs x1, CORTEX_A53_CPUACTLR_EL1 143 orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_DTAH 144 msr CORTEX_A53_CPUACTLR_EL1, x1 1451: 146 ret x17 147endfunc a53_disable_non_temporal_hint 148 149func check_errata_disable_non_temporal_hint 150 mov x1, #0x03 151 b cpu_rev_var_ls 152endfunc check_errata_disable_non_temporal_hint 153 154 /* -------------------------------------------------- 155 * Errata Workaround for Cortex A53 Errata #855873. 156 * 157 * This applies only to revisions >= r0p3 of Cortex A53. 158 * Earlier revisions of the core are affected as well, but don't 159 * have the chicken bit in the CPUACTLR register. It is expected that 160 * the rich OS takes care of that, especially as the workaround is 161 * shared with other erratas in those revisions of the CPU. 162 * Inputs: 163 * x0: variant[4:7] and revision[0:3] of current cpu. 164 * Shall clobber: x0-x17 165 * -------------------------------------------------- 166 */ 167func errata_a53_855873_wa 168 /* 169 * Compare x0 against revision r0p3 and higher 170 */ 171 mov x17, x30 172 bl check_errata_855873 173 cbz x0, 1f 174 175 mrs x1, CORTEX_A53_CPUACTLR_EL1 176 orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_ENDCCASCI 177 msr CORTEX_A53_CPUACTLR_EL1, x1 1781: 179 ret x17 180endfunc errata_a53_855873_wa 181 182func check_errata_855873 183 mov x1, #0x03 184 b cpu_rev_var_hs 185endfunc check_errata_855873 186 187/* 188 * Errata workaround for Cortex A53 Errata #835769. 189 * This applies to revisions <= r0p4 of Cortex A53. 190 * This workaround is statically enabled at build time. 191 */ 192func check_errata_835769 193 cmp x0, #0x04 194 b.hi errata_not_applies 195 /* 196 * Fix potentially available for revisions r0p2, r0p3 and r0p4. 197 * If r0p2, r0p3 or r0p4; check for fix in REVIDR, else exit. 198 */ 199 cmp x0, #0x01 200 mov x0, #ERRATA_APPLIES 201 b.ls exit_check_errata_835769 202 /* Load REVIDR. */ 203 mrs x1, revidr_el1 204 /* If REVIDR[7] is set (fix exists) set ERRATA_NOT_APPLIES, else exit. */ 205 tbz x1, #7, exit_check_errata_835769 206errata_not_applies: 207 mov x0, #ERRATA_NOT_APPLIES 208exit_check_errata_835769: 209 ret 210endfunc check_errata_835769 211 212/* 213 * Errata workaround for Cortex A53 Errata #843419. 214 * This applies to revisions <= r0p4 of Cortex A53. 215 * This workaround is statically enabled at build time. 216 */ 217func check_errata_843419 218 mov x1, #ERRATA_APPLIES 219 mov x2, #ERRATA_NOT_APPLIES 220 cmp x0, #0x04 221 csel x0, x1, x2, ls 222 /* 223 * Fix potentially available for revision r0p4. 224 * If r0p4 check for fix in REVIDR, else exit. 225 */ 226 b.ne exit_check_errata_843419 227 /* Load REVIDR. */ 228 mrs x3, revidr_el1 229 /* If REVIDR[8] is set (fix exists) set ERRATA_NOT_APPLIES, else exit. */ 230 tbz x3, #8, exit_check_errata_843419 231 mov x0, x2 232exit_check_errata_843419: 233 ret 234endfunc check_errata_843419 235 236 /* ------------------------------------------------- 237 * The CPU Ops reset function for Cortex-A53. 238 * Shall clobber: x0-x19 239 * ------------------------------------------------- 240 */ 241func cortex_a53_reset_func 242 mov x19, x30 243 bl cpu_get_rev_var 244 mov x18, x0 245 246 247#if ERRATA_A53_826319 248 mov x0, x18 249 bl errata_a53_826319_wa 250#endif 251 252#if ERRATA_A53_836870 253 mov x0, x18 254 bl a53_disable_non_temporal_hint 255#endif 256 257#if ERRATA_A53_855873 258 mov x0, x18 259 bl errata_a53_855873_wa 260#endif 261 262 /* --------------------------------------------- 263 * Enable the SMP bit. 264 * --------------------------------------------- 265 */ 266 mrs x0, CORTEX_A53_ECTLR_EL1 267 orr x0, x0, #CORTEX_A53_ECTLR_SMP_BIT 268 msr CORTEX_A53_ECTLR_EL1, x0 269 isb 270 ret x19 271endfunc cortex_a53_reset_func 272 273func cortex_a53_core_pwr_dwn 274 mov x18, x30 275 276#if !TI_AM65X_WORKAROUND 277 /* --------------------------------------------- 278 * Turn off caches. 279 * --------------------------------------------- 280 */ 281 bl cortex_a53_disable_dcache 282#endif 283 284 /* --------------------------------------------- 285 * Flush L1 caches. 286 * --------------------------------------------- 287 */ 288 mov x0, #DCCISW 289 bl dcsw_op_level1 290 291 /* --------------------------------------------- 292 * Come out of intra cluster coherency 293 * --------------------------------------------- 294 */ 295 mov x30, x18 296 b cortex_a53_disable_smp 297endfunc cortex_a53_core_pwr_dwn 298 299func cortex_a53_cluster_pwr_dwn 300 mov x18, x30 301 302#if !TI_AM65X_WORKAROUND 303 /* --------------------------------------------- 304 * Turn off caches. 305 * --------------------------------------------- 306 */ 307 bl cortex_a53_disable_dcache 308#endif 309 310 /* --------------------------------------------- 311 * Flush L1 caches. 312 * --------------------------------------------- 313 */ 314 mov x0, #DCCISW 315 bl dcsw_op_level1 316 317 /* --------------------------------------------- 318 * Disable the optional ACP. 319 * --------------------------------------------- 320 */ 321 bl plat_disable_acp 322 323 /* --------------------------------------------- 324 * Flush L2 caches. 325 * --------------------------------------------- 326 */ 327 mov x0, #DCCISW 328 bl dcsw_op_level2 329 330 /* --------------------------------------------- 331 * Come out of intra cluster coherency 332 * --------------------------------------------- 333 */ 334 mov x30, x18 335 b cortex_a53_disable_smp 336endfunc cortex_a53_cluster_pwr_dwn 337 338#if REPORT_ERRATA 339/* 340 * Errata printing function for Cortex A53. Must follow AAPCS. 341 */ 342func cortex_a53_errata_report 343 stp x8, x30, [sp, #-16]! 344 345 bl cpu_get_rev_var 346 mov x8, x0 347 348 /* 349 * Report all errata. The revision-variant information is passed to 350 * checking functions of each errata. 351 */ 352 report_errata ERRATA_A53_819472, cortex_a53, 819472 353 report_errata ERRATA_A53_824069, cortex_a53, 824069 354 report_errata ERRATA_A53_826319, cortex_a53, 826319 355 report_errata ERRATA_A53_827319, cortex_a53, 827319 356 report_errata ERRATA_A53_835769, cortex_a53, 835769 357 report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint 358 report_errata ERRATA_A53_843419, cortex_a53, 843419 359 report_errata ERRATA_A53_855873, cortex_a53, 855873 360 361 ldp x8, x30, [sp], #16 362 ret 363endfunc cortex_a53_errata_report 364#endif 365 366 /* --------------------------------------------- 367 * This function provides cortex_a53 specific 368 * register information for crash reporting. 369 * It needs to return with x6 pointing to 370 * a list of register names in ascii and 371 * x8 - x15 having values of registers to be 372 * reported. 373 * --------------------------------------------- 374 */ 375.section .rodata.cortex_a53_regs, "aS" 376cortex_a53_regs: /* The ascii list of register names to be reported */ 377 .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", \ 378 "cpuactlr_el1", "" 379 380func cortex_a53_cpu_reg_dump 381 adr x6, cortex_a53_regs 382 mrs x8, CORTEX_A53_ECTLR_EL1 383 mrs x9, CORTEX_A53_MERRSR_EL1 384 mrs x10, CORTEX_A53_L2MERRSR_EL1 385 mrs x11, CORTEX_A53_CPUACTLR_EL1 386 ret 387endfunc cortex_a53_cpu_reg_dump 388 389declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \ 390 cortex_a53_reset_func, \ 391 cortex_a53_core_pwr_dwn, \ 392 cortex_a53_cluster_pwr_dwn 393